公开(公告)号：JPS6180374A

公开(公告)日：1986-04-23

申请号：JP19701784

申请日：1984-09-21

Applicant: Ibm

Inventor： SAKAGAMI YOSHIISA ,  SUGIMOTO KAZUTOSHI

IPC: G06T5/30

CPC classification number: G06K9/44 ,  G06T5/30

公开(公告)号：JPH065824A

公开(公告)日：1994-01-14

申请号：JP3215193

申请日：1993-02-22

Applicant: IBM

Inventor： KUROODO RUI BERUTAN ,  DONETSURI JIYOOZEFU DEI MARIA ,  MIYAGAWA KIYOSHI ,  SAKAGAMI YOSHIISA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To manufacture an integrated circuit with the maximum circuit density by providing at least two vertical type direct writing EEPROM cells, that are paired each in at least one control gate in a trench that is formed in a semiconductor substrate. CONSTITUTION: A shallow trench 30 with dimensions and a configuration for accommodating at least one three-dimensional direct writing EEPROM memory cell 34 is formed in a substrate material 32, and a continuous recall gate RG is arranged at the bottom of each trench 30. Also, a discontinuous floating gate FG is provided along two sidewall parts of each trench 30, and at the same time, a program gate PG is provided at the upper part of each trench 30, thus demarcating the EEPROM cell 34 by the gates FG, RG, and PG. The program PG is mutually connected via a control gate (word line) that runs at a right angle to the trench 30. Then, a common (N ) diffused region 42 is provided between the trenches 30 in the substrate 32.