公开(公告)号：JPH0845871A

公开(公告)日：1996-02-16

申请号：JP13017395

申请日：1995-05-29

Applicant: IBM

Inventor： KUROODO RUI BERUTAN ,  UEIN JIYON HAUERU ,  KENESU EDOWAADO BAIRUSHIYUTAIN

IPC: H01L21/28 ,  H01L21/98 ,  H01L25/065

Abstract: PURPOSE: To simultaneously form metal coating on a plurality of electronic modules by using a work piece corresponding to selected side surfaces of a plurality of electronic modules on the same plane between adjacent stacked electronic modules, and cutting a metal coating pattern in a region on a plane different from the side surfaces. CONSTITUTION: A work piece 12 is completed with temporary adhesive 24 on an exposed surface of a separation material layer 22. A plurality of semiconductor chips 10 are deposited such that a flat main surface of each chip is opposite to that of adjacent chip. A long stack structure 28 extends horizontally or vertically, including a plurality of work pieces 12 each between two adjacent semiconductor chips 10. Next, the separation material layer 22 is removed from selected side surfaces of the stack structure to form grooves 32 in the long stack structure, to eliminate side-surface interruption regions from the work pieces. Next, the selected side surfaces of the long stack structure are coated with metal coating 34. The metal coating is automatically interrupted in the grooves 32 of the work pieces.

公开(公告)号：JPH065824A

公开(公告)日：1994-01-14

申请号：JP3215193

申请日：1993-02-22

Applicant: IBM

Inventor： KUROODO RUI BERUTAN ,  DONETSURI JIYOOZEFU DEI MARIA ,  MIYAGAWA KIYOSHI ,  SAKAGAMI YOSHIISA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To manufacture an integrated circuit with the maximum circuit density by providing at least two vertical type direct writing EEPROM cells, that are paired each in at least one control gate in a trench that is formed in a semiconductor substrate. CONSTITUTION: A shallow trench 30 with dimensions and a configuration for accommodating at least one three-dimensional direct writing EEPROM memory cell 34 is formed in a substrate material 32, and a continuous recall gate RG is arranged at the bottom of each trench 30. Also, a discontinuous floating gate FG is provided along two sidewall parts of each trench 30, and at the same time, a program gate PG is provided at the upper part of each trench 30, thus demarcating the EEPROM cell 34 by the gates FG, RG, and PG. The program PG is mutually connected via a control gate (word line) that runs at a right angle to the trench 30. Then, a common (N ) diffused region 42 is provided between the trenches 30 in the substrate 32.

公开(公告)号：JPH0613583A

公开(公告)日：1994-01-21

申请号：JP3189093

申请日：1993-02-22

Applicant: IBM

Inventor： ARUBAATO SUTEIIBUN BERUGENDAAR ,  KUROODO RUI BERUTAN ,  JIYON EDOWAADO KUROONIN ,  HAWAADO REO KARUTAA ,  DONARUDO MAKARUPAIN KENII ,  CHIYUN HON RAMU ,  SHIN SAN RII

IPC: H01L27/10 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a shadow RAM, which occupies only 120% or less of the space of only a DRAM by using an EEPROM in a trench in the array of the DRAM. CONSTITUTION: A memory capacitor 3 of the deep trench of polysilicon is arranged between a word line 1 and a bit line, where its contact 2 is shown. An insulating region 4 of a shallow trench is located between a pair of the deep-trench memory capacitors 3 neighboring the contact 2 and blocks stray surface currents. An EEPROM trench includes a series of discontinuous polysilicon floating gates 5, a continuous polysilicon recall-gate extending part 6, a continuous polysilicon program gate, a silicon oxide layer 8 for insulation and a dielectric spacer 7 having abundant silicon between the floating gate 5 and the recall-gate extending part 6, and between the floating gate and the program gate.