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    Power Semiconductor Module and Method for Producing a Power Semiconductor Module
    1.
    发明申请
    Power Semiconductor Module and Method for Producing a Power Semiconductor Module 审中-公开

    公开(公告)号：US20200183056A1

    公开(公告)日：2020-06-11

    申请号：US16704873

    申请日：2019-12-05

    Applicant: Infineon Technologies AG

    Inventor： Ivan Nikitin ,  Dirk Ahlers ,  Andreas Grassmann ,  Andre Uhlemann

    IPC: G02B1/118 ,  H05K3/40

    Abstract: A power semiconductor module includes a first substrate, wherein the first substrate includes aluminum, a first aluminum oxide layer arranged on the first substrate, a conductive layer arranged on the first aluminum oxide layer, a first semiconductor chip, wherein the first semiconductor chip is arranged on the conductive layer and is electrically connected thereto, and an electrical insulation material enclosing the first semiconductor chip, wherein the first aluminum oxide layer is configured to electrically insulate the first semiconductor chip from the first substrate.

    Semiconductor Device Including an Integrated Resistor
    2.
    发明申请
    Semiconductor Device Including an Integrated Resistor 审中-公开

    公开(公告)号：US20200152621A1

    公开(公告)日：2020-05-14

    申请号：US16744693

    申请日：2020-01-16

    Applicant: Infineon Technologies AG

    Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

    IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.

    Semiconductor Device Including an Integrated Resistor
    3.
    发明申请
    Semiconductor Device Including an Integrated Resistor 审中-公开

    公开(公告)号：US20190157259A1

    公开(公告)日：2019-05-23

    申请号：US16236741

    申请日：2018-12-31

    Applicant: Infineon Technologies AG

    Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

    IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78

    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area.

    DUAL GATE MOSFET DEVICES AND PRE-CHARGING TECHNIQUES FOR DC LINK CAPACITORS
    4.
    发明公开
    DUAL GATE MOSFET DEVICES AND PRE-CHARGING TECHNIQUES FOR DC LINK CAPACITORS 审中-公开

    公开(公告)号：US20240007084A1

    公开(公告)日：2024-01-04

    申请号：US17810163

    申请日：2022-06-30

    Applicant: Infineon Technologies AG

    Inventor： Dirk Ahlers ,  Manuel Wilke ,  Benjamin Schmidt ,  Jonas Groenvall

    IPC: H03K3/011 ,  H03K17/687

    CPC classification number: H03K3/011 ,  H03K17/6871

    Abstract: This disclosure is directed to a dual gate metal oxide semiconductor field effect transistor (MOSFET) device formed in a semiconductor material, as well as circuits and techniques for using the dual gate MOSFET device. In some examples, the dual gate MOSFET device may comprise a first MOSFET formed in the semiconductor material, and a second MOSFET formed in the semiconductor material, wherein the first MOSFET and the second MOSFET are arranged in parallel in the semiconductor material, wherein the first MOSFET and the second MOSFET include a common drain node and a common source node, and wherein the first MOSFET and the second MOSFET define different transfer characteristics.

    Semiconductor package having leads with a negative standoff
    5.
    发明授权
    Semiconductor package having leads with a negative standoff 有权

    公开(公告)号：US11101201B2

    公开(公告)日：2021-08-24

    申请号：US16289972

    申请日：2019-03-01

    Applicant: Infineon Technologies AG

    Inventor： Thomas Stoek ,  Dirk Ahlers ,  Stefan Macheiner

    IPC: H01L23/495 ,  H01L23/42 ,  H01L23/31

    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.

    Semiconductor Package Having Leads with a Negative Standoff
    6.
    发明申请
    Semiconductor Package Having Leads with a Negative Standoff 审中-公开

    公开(公告)号：US20200279795A1

    公开(公告)日：2020-09-03

    申请号：US16289972

    申请日：2019-03-01

    Applicant: Infineon Technologies AG

    Inventor： Thomas Stoek ,  Dirk Ahlers ,  Stefan Macheiner

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/42

    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.

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