公开(公告)号：US20170117370A1

公开(公告)日：2017-04-27

申请号：US15401146

申请日：2017-01-09

Applicant: Infineon Technologies AG

Inventor： Hubert Rothleitner

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/408 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7823 ,  H01L29/7833 ,  H01L29/7835

Abstract: A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

公开(公告)号：US20160380063A1

公开(公告)日：2016-12-29

申请号：US15189147

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Anton Mauder ,  Hermann Gruber ,  Hubert Rothleitner ,  Andreas Peter Meiser

IPC: H01L29/40

CPC classification number: H01L29/407 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823481 ,  H01L23/481 ,  H01L24/16 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/16245 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

Abstract translation: 提供一种半导体元件的制造方法。 该方法包括：提供具有与第一表面相对的第一表面和第二表面的半导体本体，将绝缘沟槽从第一表面部分地蚀刻到半导体本体中，在绝缘沟槽的一个或多个侧壁上形成第一绝缘层， 通过研磨，抛光和CMP工艺中的至少一个来处理第二表面以暴露第一绝缘层，以及在经处理的第二表面上沉积延伸到第一绝缘层的第二绝缘层。

公开(公告)号：US09577039B2

公开(公告)日：2017-02-21

申请号：US14585211

申请日：2014-12-30

Applicant: Infineon Technologies AG

Inventor： Hubert Rothleitner

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/408 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7823 ,  H01L29/7833 ,  H01L29/7835

Abstract: A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

Abstract translation: 公开了一种用于在弱反转或次阈值范围内匹配操作的MOS晶体管结构（例如，运算放大器，比较器和/或电流镜的输入对）。 晶体管结构可以包括衬底中的任何杂质类型的阱区（包括SOI）。 该区域甚至可以由衬底本身表示。 至少一个晶体管位于阱区中，由此晶体管的有源沟道区独立于GOX（栅极氧化物）和FOX（场氧化物;包括STI-浅沟槽隔离）之间的横向隔离接口。

公开(公告)号：US09761595B2

公开(公告)日：2017-09-12

申请号：US13772409

申请日：2013-02-21

Applicant: Infineon Technologies AG

Inventor： Hubert Rothleitner

IPC: G11C16/04 ,  H01L27/112 ,  G11C17/16 ,  H01L29/423

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L29/4238

Abstract: A one-time programming device includes a field effect semiconductor transistor with a gate or a channel region of the field effect semiconductor transistor including a shape of a footprint so that in an on-state of the field effect semiconductor transistor a critical electrical field is reached within an area of the channel region, a bulk region or a drain region of the field effect semiconductor transistor due to the shape of the footprint resulting in a damage of a p-n junction between the channel region or the bulk region and the drain region of the field effect semiconductor transistor or resulting in a damage of a gate insulation of the field effect semiconductor transistor after a predetermined programming time.

公开(公告)号：US20160190248A1

公开(公告)日：2016-06-30

申请号：US14585211

申请日：2014-12-30

Applicant: Infineon Technologies AG

Inventor： Hubert Rothleitner

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L29/408 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7823 ,  H01L29/7833 ,  H01L29/7835

Abstract: A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-minor) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

Abstract translation: 公开了用于弱反转或次阈值范围（例如运算放大器，比较器和/或当前次要输入对）中的匹配操作的MOS晶体管结构。 晶体管结构可以包括衬底中的任何杂质类型的阱区（包括SOI）。 该区域甚至可以由衬底本身表示。 至少一个晶体管位于阱区中，由此晶体管的有源沟道区独立于GOX（栅极氧化物）和FOX（场氧化物;包括STI-浅沟槽隔离）之间的横向隔离接口。

公开(公告)号：US20140231895A1

公开(公告)日：2014-08-21

申请号：US13772409

申请日：2013-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hubert Rothleitner

IPC: H01L29/788

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L29/4238

Abstract: A one-time programming device includes a field effect semiconductor transistor with a gate or a channel region of the field effect semiconductor transistor including a shape of a footprint so that in an on-state of the field effect semiconductor transistor a critical electrical field is reached within an area of the channel region, a bulk region or a drain region of the field effect semiconductor transistor due to the shape of the footprint resulting in a damage of a p-n junction between the channel region or the bulk region and the drain region of the field effect semiconductor transistor or resulting in a damage of a gate insulation of the field effect semiconductor transistor after a predetermined programming time.

Abstract translation: 一次性编程装置包括具有场效应半导体晶体管的栅极或沟道区域的场效应半导体晶体管，其包括占空比的形状，使得在场效应半导体晶体管的导通状态中达到临界电场 在沟道区域的区域内，场效应半导体晶体管的体区域或漏极区域由于覆盖区的形状而导致沟道区域或块区域与漏极区域之间的pn结的损坏 场效应半导体晶体管，或者在预定的编程时间之后导致场效应半导体晶体管的栅极绝缘的损坏。