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公开(公告)号：US10453742B2
公开(公告)日：2019-10-22
申请号：US15993029
申请日：2018-05-30
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer
IPC: H01L21/768 , H01L23/00 , H01L25/07 , H01L23/66 , H01L23/538 , H01L23/64 , H01L23/367 , H02M7/00 , H05K3/46
Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.
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公开(公告)号：US10374439B2
公开(公告)日：2019-08-06
申请号：US15005432
申请日：2016-01-25
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer , Johannes Teigelkoetter
Abstract: A circuit arrangement includes a power semiconductor circuit, a first charge storage unit and a second charge storage unit. The first charge storage unit has first and second terminals, the second charge storage unit has first and second terminals, and the power semiconductor circuit has first and second terminals. The power semiconductor circuit also has a first semiconductor component and a second semiconductor component, the load paths of which are electrically connected in series between the first and second terminals of the power semiconductor circuit. A first connection electrically connects the first terminal of the first charge storage unit to the first terminal of the second charge storage unit, and a second connection electrically connects the second terminal of the first charge storage unit to the second terminal of the second charge storage unit. A magnetic core is electromagnetically coupled to the first and/or second connections.
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公开(公告)号：US10177057B2
公开(公告)日：2019-01-08
申请号：US15380656
申请日：2016-12-15
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer
Abstract: A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package includes a semiconductor die embedded in or covered by a molded plastic body, the molded plastic body satisfying only a subset of the plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package further includes a plurality of terminals protruding from the molded plastic body and electrically connected to the semiconductor die, and a coating applied to at least part of the molded plastic body and/or part of the plurality of terminals. The coating satisfies each predetermined electrical, mechanical, chemical and/or environmental requirement not satisfied by the molded plastic body.
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公开(公告)号：US20180277425A1
公开(公告)日：2018-09-27
申请号：US15993029
申请日：2018-05-30
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer
IPC: H01L21/768 , H01L25/07 , H01L23/367 , H01L23/538 , H01L23/64 , H01L23/00 , H01L23/66
Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.
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公开(公告)号：US10032743B2
公开(公告)日：2018-07-24
申请号：US14296678
申请日：2014-06-05
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer , Winfried Luerbke
IPC: H01L21/44 , H01L29/40 , H01L23/00 , H01L23/48 , H01L21/48 , H01L23/498 , H01L23/053
Abstract: A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire. A separating location and a second section of the wire, the second section being spaced apart from the separating location, are defined on the wire. The wire is reshaped in the second section. Before or after reshaping, the wire is severed at the separating location, such that a terminal conductor of the semiconductor module is formed from a part of the wire. The terminal conductor is bonded to the metallization and having a free end at the separating location.
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Patent Agency Ranking
公开(公告)号：US20180174936A1
公开(公告)日：2018-06-21
申请号：US15380656
申请日：2016-12-15
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer
CPC classification number: H01L23/293 , C09K21/06 , H01L23/18 , H01L23/28 , H01L23/3107 , H01L23/3135 , H01L23/3142 , H01L23/3157 , H01L23/3192 , H01L2223/58
Abstract: A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package includes a semiconductor die embedded in or covered by a molded plastic body, the molded plastic body satisfying only a subset of the plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package further includes a plurality of terminals protruding from the molded plastic body and electrically connected to the semiconductor die, and a coating applied to at least part of the molded plastic body and/or part of the plurality of terminals. The coating satisfies each predetermined electrical, mechanical, chemical and/or environmental requirement not satisfied by the molded plastic body.
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公开(公告)号：US11646258B2
公开(公告)日：2023-05-09
申请号：US16944303
申请日：2020-07-31
Applicant: Infineon Technologies AG
Inventor： Edward Fuergut , Thomas Basler , Reinhold Bayerer , Ivan Nikitin
IPC: H01L23/498 , H01L23/66 , H01L21/56 , H01L21/48 , H01L23/29
CPC classification number: H01L23/49838 , H01L21/4846 , H01L21/565 , H01L23/293 , H01L23/66 , H01L2223/6605
Abstract: An electronic device and method is disclosed. In one example, the electronic device includes an electrically insulating material, a first load electrode arranged on a first surface of the electrically insulating material, and a second load electrode arranged on a second surface of the electrically insulating material opposite to the first surface, wherein the load electrodes are separated by the electrically insulating material along the entire length on which the load electrodes have opposite sections, wherein surfaces of the load electrodes facing away from the electrically insulating material are uncovered by the electrically insulating material.
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公开(公告)号：US10134654B2
公开(公告)日：2018-11-20
申请号：US15660087
申请日：2017-07-26
Applicant: Infineon Technologies AG
Inventor： Hans Hartung , Reinhold Bayerer
IPC: H01L23/48 , H01L23/31 , H01L21/52 , H01L21/56 , H01L23/053 , H01L23/29 , H01L23/373 , H01L23/538 , H01L23/00 , H01L23/24 , H01L25/07
Abstract: One aspect relates to a power semiconductor module. The module includes a module housing, a substrate, and a semiconductor chip attached to the substrate. The semiconductor chip is disposed in the module housing. A dielectric first encapsulation is disposed in the module housing, in physical contact with both the semiconductor chip and the substrate and has a first modulus of elasticity. A dielectric second encapsulation is disposed in the module housing and has a second modulus of elasticity. The first encapsulation is a polymer and disposed between the substrate and the second encapsulation. The semiconductor chip is disposed between the first encapsulation and the substrate. Further, the first modulus of elasticity is greater than the second modulus of elasticity.
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公开(公告)号：US20180286745A1
公开(公告)日：2018-10-04
申请号：US15993173
申请日：2018-05-30
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer
IPC: H01L21/768 , H01L23/66
CPC classification number: H01L21/76838 , H01L21/76877 , H01L23/367 , H01L23/5386 , H01L23/645 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/071 , H01L25/072 , H01L2223/6627 , H01L2224/05599 , H01L2224/48227 , H01L2924/00014 , H01L2924/19105 , H02M7/003 , H05K3/4608 , H05K3/4617 , H05K2201/10166 , H01L2224/45099
Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.
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公开(公告)号：US20180184538A1
公开(公告)日：2018-06-28
申请号：US15852158
申请日：2017-12-22
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer
Abstract: One aspect relates to a method for producing an electronic module assembly. According to the method, a curable first mass extending between a substrate assembly and a module housing is cured while a circuit carrier of the substrate assembly has at least a first temperature. Between a side wall of the module housing and the substrate assembly, an adhesive connection is formed by curing a curable second mass. Subsequent to curing the first mass, the circuit carrier is cooled down to below a second temperature lower than the first temperature. Embodiments of the electronic module assembly are also described.
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