公开(公告)号：US11127693B2

公开(公告)日：2021-09-21

申请号：US16710044

申请日：2019-12-11

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Katrin Albers ,  Joerg Busch ,  Klaus Goller ,  Norbert Mais ,  Marianne Kolitsch ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00 ,  B81B7/00 ,  H01L23/58

Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

公开(公告)号：US11081384B2

公开(公告)日：2021-08-03

申请号：US16388632

申请日：2019-04-18

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Joerg Busch

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/532 ,  H01L23/495

Abstract: A method includes producing a semiconductor arrangement having a semiconductor layer, a first insulation layer arranged on the semiconductor layer and facing a first surface of the semiconductor arrangement, and an insulating via extending in a vertical direction through the semiconductor layer as far as the first insulation layer, the insulating via surrounding a region of the semiconductor layer in a ring-shaped fashion. The method further includes permanently securing a first carrier to the first surface of the semiconductor arrangement.

公开(公告)号：US20190326155A1

公开(公告)日：2019-10-24

申请号：US16388632

申请日：2019-04-18

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Joerg Busch

IPC: H01L21/762 ,  H01L23/00 ,  H01L23/532 ,  H01L23/495

Abstract: A method includes producing a semiconductor arrangement having a semiconductor layer, a first insulation layer arranged on the semiconductor layer and facing a first surface of the semiconductor arrangement, and an insulating via extending in a vertical direction through the semiconductor layer as far as the first insulation layer, the insulating via surrounding a region of the semiconductor layer in a ring-shaped fashion. The method further includes permanently securing a first carrier to the first surface of the semiconductor arrangement.