公开(公告)号：US20190362772A1

公开(公告)日：2019-11-28

申请号：US16435878

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C11/4094 ,  G06F9/38 ,  G11C11/4074 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/0897 ,  G06F12/0868 ,  G06F13/40 ,  G06F3/06 ,  G06F9/30 ,  G11C11/4093

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US20190035452A1

公开(公告)日：2019-01-31

申请号：US16054207

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C11/4094 ,  G06F3/06 ,  G11C11/4093 ,  G06F13/40 ,  G06F9/38 ,  G11C11/4074

CPC classification number: G11C11/4094 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3887 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/109 ,  G06F13/4068 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10062429B1

公开(公告)日：2018-08-28

申请号：US15488681

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Bhushan Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C5/05 ,  G11C11/4094 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G06F13/40 ,  G06F9/38

CPC classification number: G11C11/4094 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3887 ,  G06F12/08 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/109 ,  G06F13/4068 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10790010B2

公开(公告)日：2020-09-29

申请号：US16435878

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/40 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0897 ,  G06F12/0868 ,  G06F12/109 ,  G06F12/1027 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G06F12/08 ,  G11C11/419

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10347324B2

公开(公告)日：2019-07-09

申请号：US16054207

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C7/00 ,  G11C11/4094 ,  G06F13/40 ,  G06F9/38 ,  G06F12/08 ,  G06F9/30 ,  G06F3/06 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/419

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.