公开(公告)号：US20250110741A1

公开(公告)日：2025-04-03

申请号：US18477790

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Jorge Eduardo Parra Osorio ,  Fangwen Fu ,  Guei-Yuan Lueh ,  Hong Jiang ,  Jiasheng Chen ,  Naveen K. Mellempudi ,  Kevin Hurd ,  Chunhui Mei ,  Alexandre Hadj-Chaib ,  Elliot Taylor ,  Shuai Mu

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus to facilitate supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that is to operate on 8-bit floating point operands to perform a parallel dot product operation; a scheduler to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and circuitry to execute the decoded instruction to perform 32-way dot-product using 8-bit wide dot-product layers, each 8-bit wide dot-product layer comprises one or more sets of interconnected multipliers, shifters, and adders, wherein each set of multipliers, shifters, and adders is to generate a dot product of the 8-bit floating point operands.

公开(公告)号：US20250110733A1

公开(公告)日：2025-04-03

申请号：US18477865

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Jorge Eduardo Parra Osorio ,  Fangwen Fu ,  Guei-Yuan Lueh ,  Jiasheng Chen ,  Naveen K. Mellempudi ,  Kevin Hurd ,  Alexandre Hadj-Chaib ,  Elliot Taylor ,  Marius Cornea-Hasegan

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An apparatus to facilitate conversion operations and special value use cases supporting 8-bit floating point format in a graphics architecture is disclosed. The apparatus includes a processor comprising a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction to cause the processor to perform conversion operation corresponding to an 8-bit floating point format operand; a scheduler to schedule the decoded instruction and provide input data for an input operand of the conversion operation indicated by the decoded instruction; and conversion circuitry to execute the decoded instruction to perform the conversion operation to convert the input operand to an output operand in accordance with the 8-bit floating point format operand, the conversion circuitry comprising hardware circuitry to rescale, normalize, and convert the input operand to the output operand.