公开(公告)号：US20190188154A1

公开(公告)日：2019-06-20

申请号：US15843165

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Rangeen Basu Roy Chowdhury ,  Hussein Elnawawy ,  Amro Awad

IPC: G06F12/126 ,  G06F12/1027 ,  G06F12/1018 ,  G06F9/30 ,  G06F9/50 ,  G06F9/455

CPC classification number: G06F12/126 ,  G06F9/3004 ,  G06F9/5016 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2009/45583 ,  G06F2212/684

Abstract: A processor includes a first translation lookaside buffer (TLB), a second TLB, and a TLB control mechanism. The TLB control mechanism is to store a TLB-miss count (TMC) for a page. The TMC indicates a number of TLB misses of the first TLB for the page. The TLB control mechanism is further to determine that the TMC is greater than a threshold count and store a translation of the page in the second TLB responsive to a determination that the TMC is greater than the threshold count.