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    Data plane interface network quality of service in multi-tenant data centers
    2.
    发明授权
    Data plane interface network quality of service in multi-tenant data centers 有权

    公开(公告)号：US11178023B2

    公开(公告)日：2021-11-16

    申请号：US15638959

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Parthasarathy Sarangam ,  Anjali Jain ,  Kevin Scott

    IPC: H04L12/24 ,  H04L12/911 ,  H04L12/927 ,  H04L12/26 ,  G06F9/50

    Abstract: Methods, apparatus, and systems for data plane interface network Quality of Service (QoS) in multi-tenant data centers. Data plane operations including packet generation and encapsulation are performed in software running in virtual machines (VMs) or containers hosted by a compute platform. Control plane operations, including QoS traffic classification, are implemented in hardware by a network controller. Work submission and work completion queues are implemented in software for each VM or container. Work elements (WEs) defining work to be completed by the network controller are generated by software and processed by the network controller to classify packets associated with the WEs into QoS traffic classes, wherein packets belonging to a give traffic flow are classified to the same QoS traffic class. The network controller is also configured to perform scheduling of packet egress as a function of the packet's QoS traffic classifications, to transmit packets that are scheduled for egress onto the network, and to DMA indicia to the work completion queues to indicate the work associated with WEs has been completed.

    ON-DEMAND PAGING SUPPORT FOR CONFIDENTIAL COMPUTING
    4.
    发明申请
    ON-DEMAND PAGING SUPPORT FOR CONFIDENTIAL COMPUTING 有权

    公开(公告)号：US20220335109A1

    公开(公告)日：2022-10-20

    申请号：US17854670

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Ravi Sahita ,  Anjali Jain ,  Reouven Elbaz

    IPC: G06F21/12 ,  G06F13/28 ,  G06F9/455

    Abstract: On-demand paging support for confidential computing is described. An example of an apparatus includes circuitry including one or more processors including a first processor, the first processor including a TEE and registers, wherein the one or more processors are to: receive a memory access request associated with a trust domain (TD), wherein one or more direct memory access payloads associated with the request being generated by a protocol engine (PE) of a peripheral device and written to a host interface (HIF), the HIF including an address translation engine (ATE); and, in response to a page fault being identified for a payload, divert the payload and forward a payload fault to one or more TD fault buffers in a set of registers, and resolve the page fault by an ATE driver and a virtual machine manager using the TEE.

    DATA PLANE INTERFACE NETWORK QUALITY OF SERVICE IN MULTI-TENANT DATA CENTERS
    5.
    发明申请
    DATA PLANE INTERFACE NETWORK QUALITY OF SERVICE IN MULTI-TENANT DATA CENTERS 有权

    公开(公告)号：US20220078089A1

    公开(公告)日：2022-03-10

    申请号：US17526961

    申请日：2021-11-15

    Applicant: Intel Corporation

    Inventor： Parthasarathy Sarangam ,  Anjali Jain ,  Kevin Scott

    IPC: H04L12/24 ,  H04L12/911 ,  H04L12/927 ,  H04L12/26

    Abstract: Methods, apparatus, and systems for data plane interface network Quality of Service (QoS) in multi-tenant data centers. Data plane operations including packet generation and encapsulation are performed in software running in virtual machines (VMs) or containers hosted by a compute platform. Control plane operations, including QoS traffic classification, are implemented in hardware by a network controller. Work submission and work completion queues are implemented in software for each VM or container. Work elements (WEs) defining work to be completed by the network controller are generated by software and processed by the network controller to classify packets associated with the WEs into QoS traffic classes, wherein packets belonging to a give traffic flow are classified to the same QoS traffic class. The network controller is also configured to perform scheduling of packet egress as a function of the packet's QoS traffic classifications, to transmit packets that are scheduled for egress onto the network, and to DMA indicia to the work completion queues to indicate the work associated with WEs has been completed.

    NETWORK LAYER 7 OFFLOAD TO INFRASTRUCTURE PROCESSING UNIT FOR SERVICE MESH
    6.
    发明申请
    NETWORK LAYER 7 OFFLOAD TO INFRASTRUCTURE PROCESSING UNIT FOR SERVICE MESH 有权

    公开(公告)号：US20220014459A1

    公开(公告)日：2022-01-13

    申请号：US17486579

    申请日：2021-09-27

    Applicant: Intel Corporation

    Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

    IPC: H04L12/751 ,  H04L12/715 ,  G06F13/28 ,  G06F13/16

    Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

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