公开(公告)号：US20240184523A1

公开(公告)日：2024-06-06

申请号：US18553185

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Bin Wang ,  Bo Peng ,  Xiaoyun Wang

IPC: G06F7/49

CPC classification number: G06F7/49

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for mixed radix fast Fourier transform (FFT) calculations of graphics processing units (GPUs). An example apparatus disclosed herein includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.

公开(公告)号：US11960887B2

公开(公告)日：2024-04-16

申请号：US17795170

申请日：2020-03-03

Applicant: Intel Corporation

Inventor： Bin Wang ,  Bo Peng

IPC: G06F9/30 ,  H04N19/00

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  H04N19/00

Abstract: Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.