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1.发明授权公开(公告)号：US11960887B2
公开(公告)日：2024-04-16
申请号：US17795170
申请日：2020-03-03
Applicant: Intel Corporation
CPC classification number: G06F9/30032 , G06F9/30036 , H04N19/00
Abstract: Techniques related to packing pieces of data having variable bit lengths to serial packed data using a graphics processing unit and a central processing unit are discussed. Such techniques include executing bit shift operations for the pieces of data in parallel via execution units of the graphics processing unit and packing the bit shifted pieces of data via the central processing unit.
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公开(公告)号：US09442723B2
公开(公告)日：2016-09-13
申请号：US13730665
申请日：2012-12-28
Applicant: Intel Corporation
CPC classification number: G06F9/3867 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3555 , G06F9/3893 , G06F15/8053
Abstract: A method is described that performing an image integral calculation by creating a second vector and creating a third vector. The second vector is created by executing a first instruction that adds alternating elements of a first vector to respective neighboring elements of the first vector and presents resulting summations into said second vector. The first instruction also passes through the respective neighboring elements to said second vector. The third vector is created by executing a second instruction that adds elements of one side of the second vector to an element of another side of the second vector and passes through the another side of the second vector.
Abstract translation: 描述了通过创建第二向量并创建第三向量来执行图像积分计算的方法。 通过执行第一指令来创建第二向量，第一指令将第一向量的交替元素添加到第一向量的相应相邻元素，并将所得到的和值呈现给所述第二向量。 第一指令还通过相应的相邻元件到达所述第二向量。 通过执行第二指令来创建第三向量，该第二指令将第二向量的一侧的元素添加到第二向量的另一侧的元素，并通过第二向量的另一侧。
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公开(公告)号：US10936766B2
公开(公告)日：2021-03-02
申请号：US15129816
申请日：2014-03-27
Applicant: INTEL CORPORATION
Inventor： Liu Yang , Qiang Li , Bin Wang , Xianchao Xu , Bing Niu
IPC: G06F17/18 , G06F30/20 , G06T7/35 , G06F30/00 , G06F111/10
Abstract: Various embodiments are generally directed to techniques for employing a hybrid of sequential and parallel processing to perform random sample and consensus (RANSAC). A device to perform RANSAC includes a derivation component to derive a first set of proposed models in parallel from a first set of minimal sample sets of a data set; and a comparison component to recalculate a required quantity of proposed models to derive an accurate model if a proposed model of the first set of proposed models better fits the data set than any proposed model derived prior to derivation of the first set of proposed models, and to determine whether to derive a second set of proposed models following derivation of the first set of proposed models based on a comparison of the required quantity to a quantity of previously derived proposed models that includes the first set. Other embodiments are described and claimed.
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公开(公告)号：US20200264626A1
公开(公告)日：2020-08-20
申请号：US16639702
申请日：2017-09-27
Applicant: Intel Corporation
Inventor： Bin Wang , Jianguo Li , Shoumeng Yan
Abstract: Autonomous robots and methods of operating the same are disclosed. An autonomous robot includes a sensor and memory including machine readable instructions. The autonomous robot further includes at least one processor to execute the instructions to generate a velocity costmap associated with an environment in which the robot is located. The processor generates the velocity costmap based on a source image captured by the sensor. The velocity costmap includes velocity information indicative of movement of an obstacle detected in the environment.
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公开(公告)号：US09766897B2
公开(公告)日：2017-09-19
申请号：US15264572
申请日：2016-09-13
Applicant: Intel Corporation
CPC classification number: G06F9/3867 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3555 , G06F9/3893 , G06F15/8053
Abstract: A method is described that performing an image integral calculation by creating a second vector and creating a third vector. The second vector is created by executing a first instruction that adds alternating elements of a first vector to respective neighboring elements of the first vector and presents resulting summations into said second vector. The first instruction also passes through the respective neighboring elements to said second vector. The third vector is created by executing a second instruction that adds elements of one side of the second vector to an element of another side of the second vector and passes through the another side of the second vector.
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Patent Agency Ranking
公开(公告)号：US20170140078A1
公开(公告)日：2017-05-18
申请号：US15129816
申请日：2014-03-27
Applicant: INTEL CORPORATION
Inventor： Liu Yang , Qiang Li , Bin Wang , Xianchao Xu , Bing Niu
CPC classification number: G06F17/5009 , G06F17/18 , G06F17/50 , G06F2217/16 , G06T7/35
Abstract: Various embodiments are generally directed to techniques for employing a hybrid of sequential and parallel processing to perform random sample and consensus (RANSAC). A device to perform RANSAC includes a derivation component to derive a first set of proposed models in parallel from a first set of minimal sample sets of a data set; and a comparison component to recalculate a required quantity of proposed models to derive an accurate model if a proposed model of the first set of proposed models better fits the data set than any proposed model derived prior to derivation of the first set of proposed models, and to determine whether to derive a second set of proposed models following derivation of the first set of proposed models based on a comparison of the required quantity to a quantity of previously derived proposed models that includes the first set. Other embodiments are described and claimed.
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7.发明公开公开(公告)号：US20240184523A1
公开(公告)日：2024-06-06
申请号：US18553185
申请日：2021-06-24
Applicant: Intel Corporation
Inventor： Bin Wang , Bo Peng , Xiaoyun Wang
IPC: G06F7/49
CPC classification number: G06F7/49
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for mixed radix fast Fourier transform (FFT) calculations of graphics processing units (GPUs). An example apparatus disclosed herein includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.
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公开(公告)号：US11334086B2
公开(公告)日：2022-05-17
申请号：US16639702
申请日：2017-09-27
Applicant: Intel Corporation
Inventor： Bin Wang , Jianguo Li , Shoumeng Yan
Abstract: Autonomous robots and methods of operating the same are disclosed. An autonomous robot includes a sensor and memory including machine readable instructions. The autonomous robot further includes at least one processor to execute the instructions to generate a velocity costmap associated with an environment in which the robot is located. The processor generates the velocity costmap based on a source image captured by the sensor. The velocity costmap includes velocity information indicative of movement of an obstacle detected in the environment.
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公开(公告)号：US10121090B2
公开(公告)日：2018-11-06
申请号：US15125027
申请日：2014-04-11
Applicant: Intel Corporation
Inventor： Jianguo Li , Ke Chen , Yi-Jen Chiu , Chen Wang , Ya-Ti Peng , Bin Wang
Abstract: Techniques related to object detection using directional filtering are discussed. Such techniques may include determining directional weighted averages for pixels of an input image, generating a feature representation of the input image based on the directional weighted averages, and performing object detection by applying a multi-stage cascade classifier to the feature representation.
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公开(公告)号：US09317768B2
公开(公告)日：2016-04-19
申请号：US13625962
申请日：2012-09-25
Applicant: Intel Corporation
IPC: G06K9/46
CPC classification number: G06K9/46
Abstract: Techniques for improved feature detection are described. In one embodiment, for example, a device may include a processor circuit and a feature detection module, and the feature detection module may be operative on the processor circuit to perform a first feature detection iteration for a graphics information element using an integral pixel value array, determine a scaling factor, recalculate the integral pixel value array based on the scaling factor, and perform a second feature detection iteration for the graphics information element using the recalculated integral pixel value array. Other embodiments are described and claimed.
Abstract translation: 描述了用于改进特征检测的技术。 在一个实施例中，例如，设备可以包括处理器电路和特征检测模块，并且特征检测模块可以在处理器电路上操作，以使用积分像素值阵列来执行图形信息元素的第一特征检测迭代 确定缩放因子，基于缩放因子重新计算积分像素值阵列，并且使用重新计算的积分像素值阵列对图形信息元素执行第二特征检测迭代。 描述和要求保护其他实施例。
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