公开(公告)号：US20240061683A1

公开(公告)日：2024-02-22

申请号：US18239106

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Robert C. VALENTINE ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Robert D. CAVIN ,  Bret L. TOLL ,  Santiago Galan DURAN ,  Jeffrey G. WIEDEMEIER ,  Sridhar SAMUDRALA ,  Milind Baburao GIRKAR ,  Edward Thomas GROCHOWSKI ,  Jonathan Cannon HALL ,  Dennis R. BRADFORD ,  Elmoustapha OULD-AHMED-VALL ,  James C ABEL ,  Mark CHARNEY ,  Seth ABRAHAM ,  Suleyman SAIR ,  Andrew Thomas FORSYTH ,  Lisa WU ,  Charles YOUNT

IPC: G06F9/30 ,  G06F9/34 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/34 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78696 ,  G06F9/30018 ,  H01L29/66

Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

公开(公告)号：US20210349720A1

公开(公告)日：2021-11-11

申请号：US17382917

申请日：2021-07-22

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Stanislav SHWARTSMAN ,  Dan BAUM ,  Igor YANOVER ,  Elmoustapha OULD-AHMED-VALL ,  Menachem ADELMAN ,  Jesus CORBAL ,  Yuri GEBIL ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

公开(公告)号：US20210216325A1

公开(公告)日：2021-07-15

申请号：US17216580

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Bret L. TOLL ,  Buford M. GUY ,  Ronak SINGHAL ,  Mishali NAIK

IPC: G06F9/30

Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US20200241873A1

公开(公告)日：2020-07-30

申请号：US16487784

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Stanislav SHWARTSMAN

IPC: G06F9/30 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

公开(公告)号：US20200233667A1

公开(公告)日：2020-07-23

申请号：US16487787

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Stanislav SHWARTSMAN ,  Dan BAUM ,  Igor YANOVER ,  Elmoustapha OULD-AHMED-VALL ,  Menachem ADELMAN ,  Jesus CORBAL ,  Yuri GEBIL ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

公开(公告)号：US20240111533A1

公开(公告)日：2024-04-04

申请号：US18534012

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Dan BAUM ,  Alexander F. HEINECKE ,  Elmoustaha OULD-AHMED-VALL ,  Yuri GEBIL ,  Raanan SADE

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US20220300286A1

公开(公告)日：2022-09-22

申请号：US17833643

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Stanislav SHWARTSMAN

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

公开(公告)号：US20220291926A1

公开(公告)日：2022-09-15

申请号：US17706413

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Stanislav SHWARTSMAN ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Dan BAUM ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

公开(公告)号：US20220236989A1

公开(公告)日：2022-07-28

申请号：US17587637

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Dan BAUM ,  Alexander HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.

公开(公告)号：US20200233665A1

公开(公告)日：2020-07-23

申请号：US16487747

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Dan BAUM ,  Alexander HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F17/16

Abstract: Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.