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    APPARATUSES, METHODS, AND SYSTEMS TO PRECISELY MONITOR MEMORY STORE ACCESSES
    3.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS TO PRECISELY MONITOR MEMORY STORE ACCESSES 审中-公开

    公开(公告)号：US20230176870A1

    公开(公告)日：2023-06-08

    申请号：US18160600

    申请日：2023-01-27

    Applicant: Intel Corporation

    Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

    IPC: G06F9/30 ,  G06F9/54 ,  G06F11/34 ,  G06F11/30

    CPC classification number: G06F9/30145 ,  G06F9/544 ,  G06F11/348 ,  G06F9/546 ,  G06F11/3037 ,  G06F9/30098

    Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

    APPARATUSES, METHODS, AND SYSTEMS TO PRECISELY MONITOR MEMORY STORE ACCESSES
    5.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS TO PRECISELY MONITOR MEMORY STORE ACCESSES 有权

    公开(公告)号：US20210200547A1

    公开(公告)日：2021-07-01

    申请号：US16729374

    申请日：2019-12-28

    Applicant: Intel Corporation

    Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

    IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30

    Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

    APPARATUSES, METHODS, AND SYSTEMS TO ACCELERATE STORE PROCESSING
    7.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS TO ACCELERATE STORE PROCESSING 审中-公开

    公开(公告)号：US20240211262A1

    公开(公告)日：2024-06-27

    申请号：US18419059

    申请日：2024-01-22

    Applicant: Intel Corporation

    Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

    IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F11/348

    Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

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