公开(公告)号：US20220310605A1

公开(公告)日：2022-09-29

申请号：US17839338

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/778 ,  H01L29/78

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US20200335501A1

公开(公告)日：2020-10-22

申请号：US16957664

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/778 ,  H01L29/06 ,  H01L29/78

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US20200235092A1

公开(公告)日：2020-07-23

申请号：US16647688

申请日：2018-01-08

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Cheng-ying Huang ,  Gilbert Dewey ,  Willy Rachmady ,  Rishabh Mehandru

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.

公开(公告)号：US11387238B2

公开(公告)日：2022-07-12

申请号：US16957664

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/778 ,  H01L29/06 ,  H01L29/78

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US11935891B2

公开(公告)日：2024-03-19

申请号：US17839338

申请日：2022-06-13

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L29/06 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L25/074 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/7782 ,  H01L29/785

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US11075198B2

公开(公告)日：2021-07-27

申请号：US16647688

申请日：2018-01-08

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Cheng-ying Huang ,  Gilbert Dewey ,  Willy Rachmady ,  Rishabh Mehandru

IPC: H01L25/065 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8234

Abstract: An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.