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    Forksheet transistors with dielectric or conductive spine
    3.
    发明授权
    Forksheet transistors with dielectric or conductive spine 有权

    公开(公告)号：US12243875B2

    公开(公告)日：2025-03-04

    申请号：US18409519

    申请日：2024-01-10

    Applicant: Intel Corporation

    Inventor： Seung Hoon Sung ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Christopher M. Neumann ,  Susmita Ghose ,  Varun Mishra ,  Cory Weber ,  Stephen M. Cea ,  Tahir Ghani ,  Jack T. Kavalieros

    IPC: H01L27/12 ,  H01L21/84

    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

    FORKSHEET TRANSISTOR DEVICE WITH AIR GAP SPINE
    5.
    发明公开
    FORKSHEET TRANSISTOR DEVICE WITH AIR GAP SPINE 审中-公开

    公开(公告)号：US20230163168A1

    公开(公告)日：2023-05-25

    申请号：US17455938

    申请日：2021-11-22

    Applicant: Intel Corporation

    Inventor： Ashish Agrawal ,  Christopher M. Neumann ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Jack T. Kavalieros

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L29/66795 ,  H01L29/785

    Abstract: Techniques are provided herein to form a forksheet device with an air gap spine. The air gap may be devoid of gas, or not. In an example, the device includes a first semiconductor body laterally extending from a first side of a void (air gap) and having an end surface that defines part of the first side of the void, and a second semiconductor body laterally extending from a second side of the void and having an end surface that defines part of the second side of the void. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. In some cases, a spacer structure is between a source or drain region and the corresponding gate structure, the spacer structure including one or more portions of the void. The void may be created with a backside process, post-device formation.

    FORKSHEET TRANSISTOR WITH ASYMMETRIC DIELECTRIC SPINE
    6.
    发明申请
    FORKSHEET TRANSISTOR WITH ASYMMETRIC DIELECTRIC SPINE 有权

    公开(公告)号：US20230126135A1

    公开(公告)日：2023-04-27

    申请号：US17509223

    申请日：2021-10-25

    Applicant: Intel Corporation

    Inventor： Christopher M. Neumann ,  Ashish Agrawal ,  Seung Hoon Sung ,  Marko Radosavljevic ,  Jack T. Kavalieros

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088

    Abstract: Techniques are provided herein to form a forksheet transistor device with a dielectric overhang structure. The dielectric overhang structure includes a dielectric layer that at least partially hangs over the nanoribbons of each semiconductor device in the forksheet transistor and is directly coupled to, or is an integral part of, the dielectric spine between the semiconductor devices. The overhang structure allows for a higher alignment tolerance when forming different work function metals over each of the different semiconductor devices, which in turn allows for narrower dielectric spines to be used. A first gate structure that includes a first work function metal may be formed around the nanoribbons of the n-channel device and a second gate structure that includes a second work function metal may be formed around the nanoribbons of the p-channel device in the forksheet arrangement.

    FERROELECTRIC CAPACITOR WITHIN BACKSIDE INTERCONNECT
    8.
    发明公开
    FERROELECTRIC CAPACITOR WITHIN BACKSIDE INTERCONNECT 审中-公开

    公开(公告)号：US20240114694A1

    公开(公告)日：2024-04-04

    申请号：US17937043

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Sourav Dutta ,  Nazila Haratipour ,  Uygar E. Avci ,  Vachan Kumar ,  Christopher M. Neumann ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Brian S. Doyle

    IPC: H01L27/11507

    CPC classification number: H01L27/11507

    Abstract: Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.

    Forksheet transistors with dielectric or conductive spine
    9.
    发明授权
    Forksheet transistors with dielectric or conductive spine 有权

    公开(公告)号：US11923370B2

    公开(公告)日：2024-03-05

    申请号：US17030226

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Seung Hoon Sung ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Christopher M. Neumann ,  Susmita Ghose ,  Varun Mishra ,  Cory Weber ,  Stephen M. Cea ,  Tahir Ghani ,  Jack T. Kavalieros

    IPC: H01L27/12 ,  H01L21/84

    CPC classification number: H01L27/1203 ,  H01L21/84

    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

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