公开(公告)号：US11342432B2

公开(公告)日：2022-05-24

申请号：US16833184

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US12243875B2

公开(公告)日：2025-03-04

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Christopher M. Neumann ,  Susmita Ghose ,  Varun Mishra ,  Cory Weber ,  Stephen M. Cea ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L27/12 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US12029021B2

公开(公告)日：2024-07-02

申请号：US17701419

申请日：2022-03-22

Applicant: Intel Corporation

Inventor： Peng Zheng ,  Varun Mishra ,  Tahir Ghani

IPC: H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.

公开(公告)号：US11923370B2

公开(公告)日：2024-03-05

申请号：US17030226

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Christopher M. Neumann ,  Susmita Ghose ,  Varun Mishra ,  Cory Weber ,  Stephen M. Cea ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US11862702B2

公开(公告)日：2024-01-02

申请号：US17727603

申请日：2022-04-22

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/0217 ,  H01L21/02293 ,  H01L21/02532 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1091 ,  H01L29/165 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7848 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US20240355682A1

公开(公告)日：2024-10-24

申请号：US18761493

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US12068206B2

公开(公告)日：2024-08-20

申请号：US17030449

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US20220093474A1

公开(公告)日：2022-03-24

申请号：US17030449

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L21/84 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US12288813B2

公开(公告)日：2025-04-29

申请号：US18514995

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Cory Weber ,  Willy Rachmady ,  Varun Mishra

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.

公开(公告)号：US11315934B2

公开(公告)日：2022-04-26

申请号：US16827570

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Peng Zheng ,  Varun Mishra ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/36 ,  H01L29/167 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/265

Abstract: Embodiments disclosed herein include transistor devices with depopulated channels. In an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. In an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. In an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.