公开(公告)号：US20190149134A1

公开(公告)日：2019-05-16

申请号：US16246913

申请日：2019-01-14

Applicant: Intel Corporation

Inventor： Changwon Daniel Rhee ,  Wei Xiong ,  Hongzheng Li

IPC: H03H17/02 ,  G06F17/15 ,  G06F17/16

Abstract: Various embodiments are generally directed to techniques for optimizing convolution filters. Generally, embodiments may determine, based on an analysis of a plurality of values of a convolution filter, an optimization operation to optimize at least one value of the plurality of values of the convolution filter. Embodiments may perform the optimization operation on the values of the convolution filter to generate an optimized convolution filter. Embodiments may also perform a convolution operation by a convolution logic based on the optimized convolution filter and an input data.

公开(公告)号：US20250036412A1

公开(公告)日：2025-01-30

申请号：US18358308

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Jiasheng Chen ,  Christopher Spencer ,  Jorge E. Parra Osorio ,  Kevin Hurd ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  Fangwen Fu ,  Wei Xiong ,  Hongzheng Li ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Shuai Mu ,  Clifford Gibson ,  Buqi Cheng

IPC: G06F9/30 ,  G06F9/38

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

公开(公告)号：US20250036361A1

公开(公告)日：2025-01-30

申请号：US18358304

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Jiasheng Chen ,  Kevin Hurd ,  Jorge E. Parra Osorio ,  Christopher Spencer ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  Fangwen Fu ,  Wei Xiong ,  Hongzheng Li ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Shuai Mu ,  Clifford Gibson ,  Buqi Cheng

IPC: G06F7/483

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.