公开(公告)号：US20220129323A1

公开(公告)日：2022-04-28

申请号：US17339184

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20 ,  G06F9/38

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20210382717A1

公开(公告)日：2021-12-09

申请号：US16892202

申请日：2020-06-03

Applicant: Intel Corporation

Inventor： Hong JIANG ,  Sabareesh GANAPATHY ,  Xinmin TIAN ,  Fangwen FU ,  James VALERIO

IPC: G06F9/30 ,  G06F9/52 ,  G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU) coupled to the memory device, the GPU can be configured to: execute an instruction thread; determine if a signal barrier is associated with the instruction thread; for a signal barrier associated with the instruction thread, determine if the signal barrier is cleared; and based on the signal barrier being cleared, permit any waiting instruction thread associated with the signal barrier identifier to commence with execution but not permit any waiting thread that is not associated with the signal barrier identifier to commence with execution. In some examples, the signal barrier includes a signal barrier identifier. In some examples, the signal barrier identifier is one of a plurality of values. In some examples, a gateway is used to receive indications of a signal barrier identifier and to selectively clear a signal barrier for a waiting instruction thread associated with the signal barrier identifier based on clearance conditions associated with the signal barrier being met.

公开(公告)号：US20240045725A1

公开(公告)日：2024-02-08

申请号：US17881540

申请日：2022-08-04

Applicant: Intel Corporation

Inventor： Prashant CHAUDHARI ,  Jain PHILIP ,  James VALERIO ,  Murali RAMADOSS ,  Ankur SHAH ,  Jeffery S. BOLES ,  Aditya NAVALE

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/5044 ,  G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45583

Abstract: Apparatus and method for concurrent performance monitoring. For example, one embodiment of an apparatus comprises: compute hardware logic to concurrently process a number of workloads, the compute hardware logic to be subdivided into a plurality of compute hardware contexts based on the number of workloads; and programmable performance monitoring circuitry to be dynamically partitioned to perform parallel performance monitoring operations to monitor performance of each of the plurality of compute hardware contexts while the number of workloads are concurrently processed, the programmable performance monitoring circuitry to differentiate between performance monitoring data of different compute hardware contexts based on a unique identifier associated with each of the compute hardware contexts.

公开(公告)号：US20200310883A1

公开(公告)日：2020-10-01

申请号：US16367056

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20230359499A1

公开(公告)日：2023-11-09

申请号：US18195230

申请日：2023-05-09

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/4881 ,  G06T1/20 ,  G06F9/3822 ,  G06F9/3867 ,  G06F9/5066

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20210382720A1

公开(公告)日：2021-12-09

申请号：US17131647

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sabareesh GANAPATHY ,  Fangwen FU ,  Hong JIANG ,  James VALERIO

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/48

Abstract: Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.