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公开(公告)号：US20230418612A1
公开(公告)日：2023-12-28
申请号：US17848284
申请日：2022-06-23
Applicant: Intel Corporation
Inventor： Kristof Du Bois , Wim Heirman , Stijn Eyerman , Ibrahim Hur , Jason Agron
IPC: G06F9/30
CPC classification number: G06F9/30181 , G06F9/30036
Abstract: Techniques for automatic fusion of arithmetic in-flight instructions are described. An example apparatus comprises a buffer to store instructions to be issued to a functional unit for execution, and circuitry coupled to the buffer to combine two or more instructions from the buffer into a single combined instruction. Other examples are disclosed and claimed.
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公开(公告)号：US10191745B2
公开(公告)日：2019-01-29
申请号：US15475389
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Hou-Jen Ko , Girish Venkatasubramanian , Jason Agron , Tyler Sondag , Youfeng Wu
Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.
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公开(公告)号：US20220197658A1
公开(公告)日：2022-06-23
申请号：US17128799
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Jason Agron
Abstract: An embodiment of an apparatus may comprise a memory to store configuration information, an instruction decoder to decode an instruction having one or more fields including an opcode field, and circuitry communicatively coupled to the instruction decoder and the memory, the circuitry to determine if an opcode value in the opcode field of the instruction corresponds to an altered opcode value in the stored configuration information that correlates one or more altered opcode values with respective original opcode values, and, if so determined, decode the instruction based on one of the original opcode values correlated to the altered opcode value in the stored configuration information. Other embodiments are disclosed and claimed.
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4.发明公开公开(公告)号：US20240111539A1
公开(公告)日：2024-04-04
申请号：US17957969
申请日：2022-09-30
Applicant: Intel Corporation
Inventor： Jason Agron , Andreas Kleen , Rangeen Basu Roy Chowdhury
CPC classification number: G06F9/3802 , G06F9/30189
Abstract: Techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. In an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. Based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. The page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. Based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. In another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.
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Patent Agency Ranking
公开(公告)号：US10228956B2
公开(公告)日：2019-03-12
申请号：US15282266
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Mark J. Dechene , Zhongying Zhang , Jason Agron , Sebastian Winkel
Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.
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公开(公告)号：US20180095765A1
公开(公告)日：2018-04-05
申请号：US15282266
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Mark J. Dechene , Zhongying Zhang , Jason Agron , Sebastian Winkel
CPC classification number: G06F9/455 , G06F8/443 , G06F8/4432 , G06F8/4434 , G06F8/4435 , G06F8/445 , G06F8/52 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/30181 , G06F9/30185 , G06F9/3834
Abstract: In one implementation, a processing device is provided that includes a memory to store instructions and a processor core to execute the instructions. The processor core is to receive a sequence of instructions reordered by a binary translator for execution. A first load of the sequence of instructions is identified. The first load references a memory location that stores a data item to be loaded. An occurrence of a second load is detected. The second load to access the memory location subsequent to an execution of the first load instruction. A protection field in the first load is enabled based on the detected occurrence of the second load. The enabled protection field indicates that the first load is to be checked for an aliasing associated with the memory location with respect to a subsequent store instruction. The second load is eliminated based on the enabled of the protection field.
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公开(公告)号：US12131159B2
公开(公告)日：2024-10-29
申请号：US17128799
申请日：2020-12-21
Applicant: Intel Corporation
Inventor： Jason Agron
CPC classification number: G06F9/3818 , G06F9/30101 , G06F9/30145 , G06F9/3802 , G06F21/125
Abstract: An embodiment of an apparatus may comprise a memory to store configuration information, an instruction decoder to decode an instruction having one or more fields including an opcode field, and circuitry communicatively coupled to the instruction decoder and the memory, the circuitry to determine if an opcode value in the opcode field of the instruction corresponds to an altered opcode value in the stored configuration information that correlates one or more altered opcode values with respective original opcode values, and, if so determined, decode the instruction based on one of the original opcode values correlated to the altered opcode value in the stored configuration information. Other embodiments are disclosed and claimed.
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公开(公告)号：US11061807B2
公开(公告)日：2021-07-13
申请号：US16235489
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Beeman Strong , Matthew C. Merten , Jason Agron
Abstract: A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.
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公开(公告)号：US20180285113A1
公开(公告)日：2018-10-04
申请号：US15475389
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Hou-Jen Ko , Girish Venkatasubramanian , Jason Agron , Tyler Sondag , Youfeng Wu
IPC: G06F9/30
CPC classification number: G06F9/30174 , G06F9/3016
Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.
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