公开(公告)号：US20250111579A1

公开(公告)日：2025-04-03

申请号：US18915640

申请日：2024-10-15

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20240046403A1

公开(公告)日：2024-02-08

申请号：US18231379

申请日：2023-08-08

Applicant: Intel Corporation

Inventor： Michael DOYLE ,  Travis SCHLUESSLER ,  Gabor LIKTOR ,  Atsuo KUWAHARA ,  Jefferson AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06F16/9027 ,  G06F9/3877 ,  G06F9/3891 ,  G06F9/5077 ,  G06T15/005 ,  G06T15/06

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20210287419A1

公开(公告)日：2021-09-16

申请号：US17159399

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20240013470A1

公开(公告)日：2024-01-11

申请号：US18371614

申请日：2023-09-22

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20220414970A1

公开(公告)日：2022-12-29

申请号：US17868618

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Gabor LIKTOR ,  Karthik VAIDYANATHAN ,  Jefferson AMSTUTZ ,  Atsuo KUWAHARA ,  Michael DOYLE ,  Travis SCHLUESSLER

IPC: G06T15/00 ,  G06T1/60 ,  G06T15/06

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20210241431A1

公开(公告)日：2021-08-05

申请号：US17171925

申请日：2021-02-09

Applicant: Intel Corporation

Inventor： Carson BROWNLEE ,  Ingo WALD ,  Attila AFRA ,  Johannes GUENTHER ,  Jefferson AMSTUTZ ,  Carsten BENTHIN

IPC: G06T5/00 ,  G06T1/20 ,  G06T5/20 ,  G06T9/00 ,  G06T15/06

Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.