公开(公告)号：US20230343731A1

公开(公告)日：2023-10-26

申请号：US18214742

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/66 ,  H01L23/5223 ,  H01L23/5389 ,  H01L23/5286 ,  H01L25/50 ,  H01L21/4846 ,  H01L23/5381 ,  H01L25/16 ,  H01L23/481

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US20230197682A1

公开(公告)日：2023-06-22

申请号：US18112430

申请日：2023-02-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Jianyong XIE

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/528 ,  H01L24/17 ,  H01L2924/15311

Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20200279793A1

公开(公告)日：2020-09-03

申请号：US16643816

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Jianyong XIE ,  Yidnekachew S. Mekonnen ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/66 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498

Abstract: An electronic device package is described. The electronic device package includes one or more dies. The electronic device package includes an interposer coupled to the one or more dies. The electronic device package also includes a package substrate coupled to the interposer. The electronic device package includes a plurality of through-silicon vias (TSVs) in at least one die of the one or more dies, or the interposer, or both. The electronic device package includes a passive equalizer structure communicatively coupled to a TSV pair in the plurality of TSVs. The passive equalizer structure is operable to minimize a level of insertion loss variation in the TSV pair.

公开(公告)号：US20190304935A1

公开(公告)日：2019-10-03

申请号：US15942092

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US20250112209A1

公开(公告)日：2025-04-03

申请号：US18980295

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Jianyong XIE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528

Abstract: Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20230207406A1

公开(公告)日：2023-06-29

申请号：US17561730

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Arghya SAIN ,  Andrew P. COLLINS ,  Sivaseetharaman PANDI ,  Jianyong XIE ,  Telesphor KAMGAING

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.

公开(公告)号：US20210280518A1

公开(公告)日：2021-09-09

申请号：US16810192

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Jianyong XIE ,  Sujit SHARAN ,  Huang-Ta CHEN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/64

Abstract: Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.

公开(公告)号：US20240030143A1

公开(公告)日：2024-01-25

申请号：US18377183

申请日：2023-10-05

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L23/3128 ,  H01L24/81 ,  H01L24/17 ,  H01L23/5226 ,  H01L24/13 ,  H01L23/53295 ,  H01L24/16 ,  H01L23/49822 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20230138168A1

公开(公告)日：2023-05-04

申请号：US18089542

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20220157706A1

公开(公告)日：2022-05-19

申请号：US17665315

申请日：2022-02-04

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.