公开(公告)号：US10810488B2

公开(公告)日：2020-10-20

申请号：US15385052

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Michael I Davies ,  Andrew M Lines ,  Jonathan Tse

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages.

公开(公告)号：US20180174032A1

公开(公告)日：2018-06-21

申请号：US15385052

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Michael I. Davies ,  Andrew M. Lines ,  Jonathan Tse

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/0635 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages.