公开(公告)号：US10824937B2

公开(公告)日：2020-11-03

申请号：US15385026

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Michael I. Davies

IPC: G06N3/063 ,  G06N3/04

Abstract: An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.

公开(公告)号：US20180174032A1

公开(公告)日：2018-06-21

申请号：US15385052

申请日：2016-12-20

Applicant: Intel Corporation

Inventor： Michael I. Davies ,  Andrew M. Lines ,  Jonathan Tse

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/0635 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages.

公开(公告)号：US10956811B2

公开(公告)日：2021-03-23

申请号：US15664614

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Michael I. Davies ,  Tsung-Han Lin

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: System and techniques for variable epoch spike train filtering are described herein. A spike trace storage may be initiated for an epoch. Here, the spike trace storage is included in a neural unit of neuromorphic hardware. Multiple spikes may be received at the neural unit during the epoch. The spike trace storage may be incremented for each of the multiple spikes to produce a count of received spikes. An epoch learning event may be obtained and a spike trace may be produced in response to the epoch learning event using the count of received spikes in the spike trace storage. Network parameters of the neural unit may be modified using the spike trace.

公开(公告)号：US20190034782A1

公开(公告)日：2019-01-31

申请号：US15664614

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Michael I. Davies ,  Tsung-Han Lin

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: System and techniques for variable epoch spike train filtering are described herein. A spike trace storage may be initiated for an epoch. Here, the spike trace storage is included in a neural unit of neuromorphic hardware. Multiple spikes may be received at the neural unit during the epoch. The spike trace storage may be incremented for each of the multiple spikes to produce a count of received spikes. An epoch learning event may be obtained and a spike trace may be produced in response to the epoch learning event using the count of received spikes in the spike trace storage. Network parameters of the neural unit may be modified using the spike trace.

公开(公告)号：US20210304005A1

公开(公告)日：2021-09-30

申请号：US17346842

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Michael I. Davies ,  Andrew M. Lines

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.