公开(公告)号：US09991223B2

公开(公告)日：2018-06-05

申请号：US14975532

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Russell S. Aoki ,  Michael R. Hui ,  Jonathon R. Carstens ,  Michael S. Brazel ,  Daniel P. Carter ,  Thomas A. Boyd ,  Shelby A. Ferguson ,  Rashelle Yee ,  Joseph J. Jasniewski ,  Harvey R. Kofstad ,  Anthony P. Valpiani

IPC: B23K3/08 ,  H04L23/00 ,  H01L23/00 ,  B23K1/00 ,  B23K101/42

CPC classification number: H01L24/75 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/42 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/75703 ,  H01L2224/75754 ,  H01L2224/81139 ,  H01L2224/81234 ,  H01L2924/15311 ,  H05K3/325 ,  H05K3/3436 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/166 ,  H05K2203/167 ,  Y02P70/613

Abstract: Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.

公开(公告)号：US20180350767A1

公开(公告)日：2018-12-06

申请号：US16054009

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Jonathon R. Carstens ,  Michael S. Brazel ,  Russell S. Aoki ,  Laura S. Mortimer

IPC: H01L23/00 ,  B23K1/00 ,  B23K1/008 ,  B23K1/19 ,  B23K1/20 ,  B23K3/06 ,  B23K3/08 ,  H01L23/34 ,  H01L23/498 ,  B23K101/42 ,  H05K3/12 ,  H05K3/34

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/206 ,  B23K3/06 ,  B23K3/0638 ,  B23K3/082 ,  B23K2101/42 ,  H01L23/345 ,  H01L23/49816 ,  H01L24/75 ,  H01L2224/81007 ,  H01L2224/81024 ,  H01L2224/81035 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/15321 ,  H05K3/1225 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/166

Abstract: Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA) package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is application of solder to the RGA interposer. Technical solutions described herein provide processes and equipment for application of solder and formation of solder balls to connect an RGA interposer to a BGA package.