公开(公告)号：US20240171403A1

公开(公告)日：2024-05-23

申请号：US18058475

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Karthika Murthy ,  Santosh Male ,  Girisha Dengi

IPC: H04L9/32 ,  G06K19/06

CPC classification number: H04L9/3228 ,  G06K19/06037 ,  H04L9/3247

Abstract: A system and method of implementing digitally signed secure quick response (SQR) codes include storing captured content as a hash map, calculating a hash of the captured content, where the hash is a unique key that is stored in the hash map, creating a digital signature for the captured content using a private key such that the captured content is digitally signed, generating a SQR code of the digitally signed captured content, and storing the SQR code including the digitally signed captured content in a secure digital (SD) card.

公开(公告)号：US20220335910A1

公开(公告)日：2022-10-20

申请号：US17856176

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Praveen Kashyap Ananta Bhat ,  Navneet Kumar Singh ,  Samarth Alva ,  Aiswarya Pious ,  Susanta Bhattacharjee ,  Karthika Murthy ,  Mallari Hanchate ,  Antonio Cheng

IPC: G09G5/10 ,  G06F3/0354 ,  G06F3/038 ,  G06F3/041

Abstract: Apparatus, systems, and methods for display panel power savings during stylus usage are disclosed. An example apparatus includes interface circuitry to receive touch event location data indicative of touch events by a user on a display screen of an electronic device; and processor circuitry to perform operations to instantiate display mapping circuitry to identify an area of the display screen covered by a portion of a body of the user based on a shape of the portion; and pixel identification circuitry to identify respective ones of pixels of the display screen in the area of the display screen; and cause a property of the respective ones of the pixels to be adjusted.

公开(公告)号：US20240220626A1

公开(公告)日：2024-07-04

申请号：US18147784

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Girisha Dengi ,  Karthika Murthy ,  Santosh Male

IPC: G06F21/57

CPC classification number: G06F21/575

Abstract: An apparatus includes a basic input/output system (BIOS) comprising a boot read-only memory (Boot-ROM) to load a first stage boot loader (FSBL) into a random access memory (RAM), a processor comprising at least a first processing core and a second processing core, the processor to initialize, in the first processing core, a first set of system drivers, activate, the second processing core, and load, in the second processing core, a second stage boot loader and one or more operating system images into a main system memory.

公开(公告)号：US10427065B2

公开(公告)日：2019-10-01

申请号：US15476042

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Karthika Murthy ,  Nischith Honnavar ,  Vishwa T. Kondaveeti

IPC: A63H33/04 ,  A63H33/26 ,  A63H33/08 ,  A63H33/22 ,  A63H5/00

Abstract: Techniques are disclosed for assembling a set of connectable building blocks by using a computing device to access, from wireless communication elements in each block, general information regarding the set of blocks and specific information regarding at least one block of the set that is placed on a conducting mat and each block of the set that is connected to the at least one block on the conducting mat. Structural information regarding structures for assembly using the blocks is accessed based on the general and specific information. A process for assembling a selected structure using the blocks is generated based on all of the accessed information. A lighting element of the at least one block (or a connected block) and a lighting element of at least one block of the set that is not connected to any other block of the set is made to blink based on the process.