公开(公告)号：US11494163B2

公开(公告)日：2022-11-08

申请号：US16562979

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Naveen Mellempudi ,  Dipankar Das ,  Chunhui Mei ,  Kristopher Wong ,  Dhiraj D. Kalamkar ,  Hong H. Jiang ,  Subramaniam Maiyuran ,  Varghese George

IPC: G06F7/499 ,  G06F17/16 ,  G06T1/20 ,  G06N3/04 ,  G06N3/08

Abstract: An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

公开(公告)号：US20240111825A1

公开(公告)日：2024-04-04

申请号：US17937229

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Changwon Rhee ,  Kevin Hurd ,  Gregory Henry ,  Peter Caday ,  Kristopher Wong

IPC: G06F17/16 ,  G06F7/483

CPC classification number: G06F17/16 ,  G06F7/483

Abstract: An apparatus to facilitate single precision support for systolic pipeline in a graphics environment is disclosed. The apparatus includes a processor comprising systolic array hardware including a plurality of data processing units, wherein the systolic array hardware is to: receive data for performance of a matrix multiplication operation in a first precision format; convert an original value of the data into two split values with a second precision format having a lower precision than the first precision format; perform the matrix multiplication operation using the two split values in the second precision format, the matrix multiplication operation comprising a split-term operation that utilizes two passes through the systolic array hardware with feedback wiring and local reduction; and generate an emulated result for the matrix multiplication operation in the first precision format.