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    TECHNIQUES FOR FORMING LOGIC INCLUDING INTEGRATED SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY
    3.
    发明申请
    TECHNIQUES FOR FORMING LOGIC INCLUDING INTEGRATED SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY 审中-公开
    形成逻辑的技术，包括集成的自旋转矩扭矩磁阻随机存取存储器

    公开(公告)号：WO2017171840A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2016/025585

    申请日：2016-04-01

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  GOLONZKA, Oleg ,  GHANI, Tahir ,  BRAIN, Ruth A. ,  WANG, Yih

    IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

    Abstract translation: 公开了用于形成包括集成自旋转移力矩磁阻随机存取存储器（STT-MRAM）的逻辑器件的技术。 根据一些实施例，可以在主机逻辑器件的给定后端（BEOL）互连层内形成一个或多个磁性隧道结（MTJ）器件。 根据一些实施例，给定的MTJ器件可以在被配置成用作MTJ的组成磁性和绝缘体层的基座层的导电层上形成。 根据一些实施例，可以在给定的MTJ器件和附带的基座层的侧壁上方形成一个或多个共形间隔层，从而提供对氧化和腐蚀的保护。 根据一些实施例，给定的MTJ器件可以例如通过被配置为充当薄通孔的另一居间导电层与下面的互连或其他导电特征电耦合。

    APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
    4.
    发明申请
    APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES 审中-公开
    将STT-MRAM存储阵列集成到逻辑处理器和结果结构的方法

    公开(公告)号：WO2017155508A1

    公开(公告)日：2017-09-14

    申请号：PCT/US2016/021243

    申请日：2016-03-07

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  GOLONZKA, Oleg ,  GHANI, Tahir ,  BRAIN, Ruth A. ,  WANG, Yih

    IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

    Abstract: Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.

    Abstract translation: 描述了将自旋扭矩传递磁随机存取存储器（STT-MRAM）存储器阵列集成到逻辑处理器中的方法以及所得到的结构。 在一个示例中，逻辑处理器包括逻辑区域，该逻辑区域包括布置在设置在衬底上方的介电层中的金属线/通孔对。 逻辑处理器还包括包含多个磁隧道结（MTJ）的自旋扭矩传递磁阻随机存取存储器（STT-MRAM）阵列。 MTJ被放置在电介质层中。

    HIGH DENSITY MEMORY ARRAY WITH SELF-ALIGNED VIA
    6.
    发明申请
    HIGH DENSITY MEMORY ARRAY WITH SELF-ALIGNED VIA 审中-公开
    高密度存储器阵列与自对准通过

    公开(公告)号：WO2017052586A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052210

    申请日：2015-09-25

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  WANG, Yih

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

    CPC classification number: H01L27/228 ,  H01L27/11582 ,  H01L28/00

    Abstract: An embodiment includes an apparatus comprising: a first semiconductor fin parallel to a second semiconductor fin; a first source line oblique to the first and second fins; a first contact coupling a first drain node of the first fin to a first magnetic tunnel junction (MTJ) and a second contact coupling a second drain node of the second fin to a second MTJ; wherein (a) a first vertical axis intersects the first fin and the first source line and a second vertical axis intersects the second fin and the first source line; and (b) the first contact includes sidewalls parallel to the first fin and additional sidewalls orthogonal to the first source line and the second contact includes sidewalls parallel to the second fin and additional sidewalls orthogonal to the first source line. Other embodiments are described herein.

    Abstract translation: 一个实施例包括一种装置，包括：平行于第二半导体鳍片的第一半导体鳍片; 第一源极线，倾斜于第一和第二鳍片; 将第一鳍片的第一漏极节点耦合到第一磁性隧道结（MTJ）的第一接触件和将第二鳍片的第二漏极节点耦合到第二MTJ的第二接触件; 其中（a）第一垂直轴与所述第一鳍和所述第一源极线相交，并且第二垂直轴与所述第二鳍和所述第一源极线相交; 和（b）所述第一触点包括平行于所述第一鳍片的侧壁和与所述第一源极线正交的附加侧壁，并且所述第二触点包括平行于所述第二鳍片的侧壁和与所述第一源极线正交的附加侧壁。 本文描述了其它实施例。

    PRESERVATION OF FINE PITCH REDISTRIBUTION LINES
    7.
    发明申请
    PRESERVATION OF FINE PITCH REDISTRIBUTION LINES 审中-公开
    微调重新分配线的保护

    公开(公告)号：WO2015195067A2

    公开(公告)日：2015-12-23

    申请号：PCT/US2013/048775

    申请日：2013-06-28

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  KOTHARI, Hiten ,  LYTLE, Wayne M.

    CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L2224/1182 ,  H01L2224/13565

    Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

    Abstract translation: 一个实施例包括半导体装置，其包括：再分配层（RDL），其包括具有两个RDL侧壁的图案化RDL线，所述RDL包括选自包括Cu和Au的材料; 直接接触两个RDL侧壁的保护侧壁; 包括该材料的种子层; 和阻挡层; 其中（a）所述RDL线具有与所述两个RDL侧壁正交并在所述两个RDL侧壁之间延伸的RDL线宽，并且（b）所述种子和阻挡层各自包括平行于并且宽于所述RDL线宽度的宽度。 本文描述了其它实施例。

    LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS
    8.
    发明申请
    LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS 审中-公开
    逻辑芯片，包括嵌入式磁性隧道结

    公开(公告)号：WO2014142956A1

    公开(公告)日：2014-09-18

    申请号：PCT/US2013/031994

    申请日：2013-03-15

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  GHANI, Tahir ,  STEIGERWALD, Joseph M. ,  EPPLE, John H. ,  WANG, Yih

    IPC: G11C11/15 ,  H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

    Abstract translation: 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上MTJ层，下MTJ层和直接接触上MTJ层和下MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 本文描述了其它实施例。

    MEMORY WITH HIGH OVERLAY TOLERANCE
    9.
    发明申请
    MEMORY WITH HIGH OVERLAY TOLERANCE 审中-公开
    具有高覆盖度的记忆

    公开(公告)号：WO2017052561A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052032

    申请日：2015-09-24

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J. ,  WANG, Yih

    IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12

    CPC classification number: H01L27/228

    Abstract: An embodiment includes an apparatus comprising: a first via layer between a substrate and a first metal layer; a second via layer between the first metal layer and second metal layer; a third via layer between the second metal layer and a third metal layer; and first and second access transistors each included in the substrate; wherein (a) the second via layer and the second metal layer each include portions of a first magnetic tunnel junction (MTJ) and portions of a second MTJ, (b) the third via layer includes a metal interconnect directly contacting the first and second MTJs, and (c) the third metal layer includes a bit line that couples to the first and second access transistors through the metal interconnect and the first and second MTJs. Other embodiments are described herein.

    Abstract translation: 一个实施例包括一种装置，包括：在基底和第一金属层之间的第一通孔层; 在第一金属层和第二金属层之间的第二通孔层; 在第二金属层和第三金属层之间的第三通孔层; 以及每个包括在所述衬底中的第一和第二存取晶体管; 其中（a）第二通孔层和第二金属层各自包括第一磁性隧道结（MTJ）的部分和第二MTJ的部分，（b）第三通孔层包括直接接触第一和第二MTJ的金属互连 ，和（c）第三金属层包括通过金属互连以及第一和第二MTJ耦合到第一和第二存取晶体管的位线。 本文描述了其它实施例。

    INTEGRATED CIRCUIT DIE HAVING BACKSIDE PASSIVE COMPONENTS AND METHODS ASSOCIATED THEREWITH
    10.
    发明申请
    INTEGRATED CIRCUIT DIE HAVING BACKSIDE PASSIVE COMPONENTS AND METHODS ASSOCIATED THEREWITH 审中-公开
    具有背面被动部件的集成电路和与之相关的方法

    公开(公告)号：WO2016048367A1

    公开(公告)日：2016-03-31

    申请号：PCT/US2014/057807

    申请日：2014-09-26

    Applicant: INTEL CORPORATION

    Inventor： LEE, Kevin J.

    IPC: H01L23/48

    CPC classification number: H01L25/0652 ,  H01L23/145 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例涉及集成电路（IC）裸片。 在实施例中，IC管芯可以包括半导体衬底，设置在半导体衬底的第一侧上的多个有源部件和设置在半导体衬底的第二侧上的多个无源部件。 在实施例中，第二侧可以布置成与第一侧相对。 在一些实施例中，无源部件可以包括电容器和/或电阻器，而在一些实施例中，有源部件可以包括晶体管。 可以描述和/或要求保护其他实施例。

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