公开(公告)号：US11955377B2

公开(公告)日：2024-04-09

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Robert L Bristol ,  James M. Blackwell ,  Rami Hourani ,  Marie Krysak

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0273 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76877 ,  H01L21/76897

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US11139401B2

公开(公告)日：2021-10-05

申请号：US16435359

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Rami Hourani ,  Elijah Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/11585 ,  H01L29/51 ,  H01L27/092 ,  H01L29/78

Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.

公开(公告)号：US20210143265A1

公开(公告)日：2021-05-13

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US10243080B2

公开(公告)日：2019-03-26

申请号：US15527288

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/32 ,  H01L23/498

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US10109583B2

公开(公告)日：2018-10-23

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Robert L. Bristol ,  Manish Chandhok ,  Jasmeet S. Chawla ,  Florian Gstrein ,  Eungnak Han ,  Rami Hourani ,  Kevin Lin ,  Richard E. Schenker ,  Todd R. Younkin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US20180082942A1

公开(公告)日：2018-03-22

申请号：US15560245

申请日：2015-04-29

Applicant: INTEL CORPORATION

Inventor： Jasmeet S. Chawla ,  Rami Hourani ,  Mauro J. Kobrinsky ,  Florian Gstrein ,  Scott B. Clendenning ,  Jeanette M. Roberts

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2221/101 ,  H01L2221/1063

Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

公开(公告)号：US09570349B2

公开(公告)日：2017-02-14

申请号：US15237542

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Robert L. Bristol ,  Rami Hourani ,  Eungnak Han ,  James M. Blackwell

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：US11532724B2

公开(公告)日：2022-12-20

申请号：US17154755

申请日：2021-01-21

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Szuya S. Liao ,  Florian Gstrein ,  Rami Hourani ,  Patricio E. Romero ,  Grant M. Kloster ,  Martin M. Mitan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/304 ,  H01L29/161 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775 ,  H01L21/28 ,  H01L29/49 ,  H01L21/266

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US11335598B2

公开(公告)日：2022-05-17

申请号：US16024692

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Sudipto Naskar ,  Manish Chandhok ,  Miriam Reshotko ,  Rami Hourani

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

公开(公告)号：US10756215B2

公开(公告)日：2020-08-25

申请号：US16271226

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Grant Kloster ,  Scott B. Clendenning ,  Rami Hourani ,  Szuya S. Liao ,  Patricio E. Romero ,  Florian Gstrein

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02 ,  H01L29/06 ,  H01L29/786 ,  H01L21/31 ,  H01L23/498 ,  H01L21/32 ,  H01L29/423

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.