公开(公告)号：US20250149433A1

公开(公告)日：2025-05-08

申请号：US19018705

申请日：2025-01-13

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20210327800A1

公开(公告)日：2021-10-21

申请号：US17364686

申请日：2021-06-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L23/538

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20240222137A1

公开(公告)日：2024-07-04

申请号：US18091022

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Srinivas V. PIETAMBARAM ,  Matthew L. TINGEY

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L21/3213 ,  H01L21/76808 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core, where a top surface of the TGV is not coplanar with a top surface of the core. In an embodiment, the electronic package further comprises a ridge on the top surface of the TGV, where the ridge is symmetric about a centerline of the TGV.

公开(公告)号：US20190027431A1

公开(公告)日：2019-01-24

申请号：US15654399

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.