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公开(公告)号:US11029718B2
公开(公告)日:2021-06-08
申请号:US15721521
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Matthias Eberlein
Abstract: An apparatus is provided which includes: a first supply node; a second supply node; a first transistor coupled to the first supply node, the first transistor is to provide a first current which is complementary to absolute temperature (CTAT); a second transistor coupled to the first supply node, the second transistor is to provide a second current which is proportional to absolute temperature (PTAT); a resistive device coupled in series at a node with the first and second transistors, and coupled to the second supply node, wherein the node is to sum the CTAT and the PTAT currents.
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公开(公告)号:US11015985B2
公开(公告)日:2021-05-25
申请号:US15942163
申请日:2018-03-30
Applicant: Intel Corporation
Inventor: Matthias Eberlein
Abstract: An apparatus comprises: a first circuitry to charge first and second capacitors to a predetermined voltage level; a second circuitry to discharge the first capacitor through a diode at a first time; a third circuitry to discharge the second capacitor through the diode at a second time, wherein the second time is greater than the first time; a comparator to compare a first voltage of the first capacitor with a second voltage of the second capacitor; and logic to adjust a scaling factor applied to the second voltage according to an output of the comparator.
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公开(公告)号:US11609127B2
公开(公告)日:2023-03-21
申请号:US17240861
申请日:2021-04-26
Applicant: Intel Corporation
Inventor: Matthias Eberlein
Abstract: An apparatus comprises: a first circuitry to charge first and second capacitors to a predetermined voltage level; a second circuitry to discharge the first capacitor through a diode at a first time; a third circuitry to discharge the second capacitor through the diode at a second time, wherein the second time is greater than the first time; a comparator to compare a first voltage of the first capacitor with a second voltage of the second capacitor; and logic to adjust a scaling factor applied to the second voltage according to an output of the comparator.
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公开(公告)号:US09816871B2
公开(公告)日:2017-11-14
申请号:US14865490
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: Matthias Eberlein
IPC: H01L23/58 , H01L29/10 , G01K7/01 , H01L23/34 , H01L27/02 , H01L27/06 , H01L49/02 , H01L29/78 , H01L29/861
CPC classification number: G01K7/01 , G01K7/42 , H01L23/34 , H01L27/0222 , H01L27/0629 , H01L28/00 , H01L28/60 , H01L29/785 , H01L29/861
Abstract: Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.
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公开(公告)号:US11493968B2
公开(公告)日:2022-11-08
申请号:US16537439
申请日:2019-08-09
Applicant: Intel Corporation
Inventor: Matthias Eberlein
Abstract: An apparatus is provided which generates a reverse bandgap reference using capacitive bias, which is applied to a single n-well diode. The capacitive bias allows for determining the current density precisely by pure timing control. An apparatus is also described for sensing temperature in which a forward-bias diode voltage can be sampled with a capacitor, and large current ratios are possible (e.g., ratio N greater than 1000). Duty cycle of a digital output of the sensor is used to determine the temperature sensed by the sensor.
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公开(公告)号:US20210041928A1
公开(公告)日:2021-02-11
申请号:US16537439
申请日:2019-08-09
Applicant: Intel Corporation
Inventor: Matthias Eberlein
IPC: G06F1/20 , G05F3/24 , G06F1/3203 , G01K7/01
Abstract: An apparatus is provided which generates a reverse bandgap reference using capacitive bias, which is applied to a single n-well diode. The capacitive bias allows for determining the current density precisely by pure timing control. An apparatus is also described for sensing temperature in which a forward-bias diode voltage can be sampled with a capacitor, and large current ratios are possible (e.g., ratio N greater than 1000). Duty cycle of a digital output of the sensor is used to determine the temperature sensed by the sensor.
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公开(公告)号:US10109551B2
公开(公告)日:2018-10-23
申请号:US14854487
申请日:2015-09-15
Applicant: Intel Corporation
Inventor: Cho-Ying Lu , Matthias Eberlein , Hyung-Jin Lee
Abstract: Embodiments of the present disclosure provide techniques and configurations for integrally determining a parameter (e.g., temperature) of a die of an integrated circuit. In one instance, the apparatus may comprise a die including a first (e.g., remote) area and a second (e.g., local) area disposed at a distance from the first area, and circuitry to determine a parameter associated with the remote area of the die. The circuitry may include: a first sensing device disposed in the remote area, to provide first readings associated with the parameter; a second sensing device disposed in the local area, to provide second readings associated with the parameter; and a control module coupled with the sensing devices and disposed in the local area, to facilitate a determination of the parameter based on the first and second readings provided by the first and second sensing devices. Other embodiments may be described and/or claimed.
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公开(公告)号:US10073483B2
公开(公告)日:2018-09-11
申请号:US15088345
申请日:2016-04-01
Applicant: INTEL CORPORATION
Inventor: Matthias Eberlein
Abstract: An apparatus is described having a reference voltage circuit. The reference voltage circuit includes a diode to receive first and second currents having first and second respective current densities, where, the first and second current densities are different and determined by circuitry that precisely controls the respective amount of time the first and second currents flow into the diode. The reference voltage circuit also comprises circuitry to form a reference voltage by combining first and second voltages generated from respective voltages of the diode that result from the first and second currents flowing through the diode.
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公开(公告)号:US09568929B2
公开(公告)日:2017-02-14
申请号:US14444890
申请日:2014-07-28
Applicant: INTEL CORPORATION
Inventor: Matthias Eberlein
IPC: G05F1/575
CPC classification number: G05F1/575
Abstract: Described are apparatuses and methods for generating a temperature-stabilized reference voltage on a semiconductor chip. An apparatus may include a differential amplifier including a first input, a second input, and an output. The apparatus may further include a first bipolar junction transistor (BJT) coupled to the first input; a second BJT coupled to the second input; and beta compensation circuitry, coupled to the first BJT and the second BJT, to regulate a first collector current of the first BJT to be independent of a first current gain of the first BJT and a second collector current of the second BJT to be independent of a second current gain of the second BJT. Other embodiments may be described and/or claimed.
Abstract translation: 描述了在半导体芯片上产生温度稳定的参考电压的装置和方法。 装置可以包括包括第一输入,第二输入和输出的差分放大器。 该装置还可以包括耦合到第一输入的第一双极结型晶体管(BJT); 第二个BJT耦合到第二个输入; 和β补偿电路,耦合到第一BJT和第二BJT,以调节第一BJT的第一集电极电流,以独立于第一BJT的第一电流增益和第二BJT的第二集电极电流独立于 第二个BJT的第二个电流增益。 可以描述和/或要求保护其他实施例。
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公开(公告)号:US09557226B2
公开(公告)日:2017-01-31
申请号:US14129278
申请日:2013-07-22
Applicant: INTEL CORPORATION , Matthias Eberlein
Inventor: Matthias Eberlein
Abstract: Described is a current-mode thermal sensor apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second transistor with a gate terminal coupled to a second node; a first resistor coupled to the first and second nodes; a second resistor coupled to the first node and a supply node; and a diode coupled to the second node and the supply node.
Abstract translation: 描述了一种电流模式热传感器装置,其包括:第一晶体管,其栅极端子耦合到第一节点; 第二晶体管,其栅极端子耦合到第二节点; 耦合到所述第一和第二节点的第一电阻器; 耦合到所述第一节点和供应节点的第二电阻器; 以及耦合到第二节点和供应节点的二极管。
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