公开(公告)号：US20210373833A1

公开(公告)日：2021-12-02

申请号：US16890798

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Sagar Pawar ,  Prakash Pillai ,  Ovais Pir ,  Murali Iyengar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Aneesh Tuljapurkar

IPC: G06F3/14 ,  G06F3/0487 ,  G09G3/34

Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.

公开(公告)号：US20200225994A1

公开(公告)日：2020-07-16

申请号：US16832372

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Murali R. Iyengar ,  Karunakara Kotary ,  Ovais Pir ,  Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N. ,  Aneesh A. Tuljapurkar

IPC: G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/1009 ,  G06T1/60

Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.

公开(公告)号：US20220198022A1

公开(公告)日：2022-06-23

申请号：US17132844

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Sagar C. Pawar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Prakash Pillai ,  Ovais Pir

IPC: G06F21/57 ,  G06F1/18 ,  G06F21/32 ,  G06F1/3215 ,  G06F1/26

Abstract: A power-up scheme for a computing system that applies a biometric sensor (e.g., a fingerprint sensor, eye sensor, etc.) to authenticate a user before enabling power-up of the computing system or to resume transition to a power state (e.g., one of the power states defined by the Advance Configuration and Power Interface (ACPI)). Output of the biometric sensor is compared against data of a registered user for a match. The data may include an original copy of an output of the biometric sensor saved in a non-volatile memory (e.g., serial peripheral interface (SPI) flash device). If a match exists, a logic in the computing system will allow the computing system to power-up. In the absence of a match, the computing system will not be powered up. In some examples, battery charging is also disabled if the match is not found.

公开(公告)号：US12007823B2

公开(公告)日：2024-06-11

申请号：US17702504

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

IPC: G06F1/32 ,  G06F1/3231

CPC classification number: G06F1/3231

Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

公开(公告)号：US11720401B2

公开(公告)日：2023-08-08

申请号：US16832372

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Murali R Iyengar ,  Karunakara Kotary ,  Ovais Pir ,  Sagar C Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A Tuljapurkar

IPC: G06F9/4401 ,  G06F9/50 ,  G06F9/54 ,  G06F12/1009 ,  G06T1/60

CPC classification number: G06F9/5016 ,  G06F9/4406 ,  G06F9/544 ,  G06F12/1009 ,  G06T1/60

Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.

公开(公告)号：US20220391003A1

公开(公告)日：2022-12-08

申请号：US17702504

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

IPC: G06F1/3231

Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

公开(公告)号：US12253966B2

公开(公告)日：2025-03-18

申请号：US17482786

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Prakash Pillai ,  Sagar Pawar ,  Raghavendra Nagaraj ,  Ovais Pir ,  Pannerkumar Rajagopal

IPC: G06F11/07 ,  G06F9/445 ,  G06F13/42

Abstract: A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.

公开(公告)号：US20220206591A1

公开(公告)日：2022-06-30

申请号：US17698712

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Sagar Pawar ,  Raghavendra Nagaraj ,  Prakash Pillai ,  Ovais Pir ,  Pannerkumar Rajagopal

IPC: G06F3/023 ,  G06F3/02

Abstract: Methods and apparatus for adaptive keyboard scanning are disclosed. A disclosed example apparatus to adaptively control operation of a keyboard includes at least one memory, instructions, and processor circuitry. The processor circuitry is to determine whether to operate the keyboard in a first mode or in a second mode different from the first mode, the first mode corresponding to a first number of keys, the second mode corresponding to a second number of keys less than the first number of keys, and set the keyboard to operate in the first mode or the second mode based on the determination.