公开(公告)号：US10863138B2

公开(公告)日：2020-12-08

申请号：US15169262

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： Vidhya Krishnan ,  Balaji Vembu ,  Sandeep S. Sodhi ,  Priyadarsini Devanand

IPC: H04N7/167 ,  H04L9/06 ,  H04N21/2347

Abstract: Apparatuses, methods and storage medium associated with single pass parallel encryption are disclosed herein. In embodiments, an apparatus for computing may comprise an encryption engine to encrypt a video stream. The encryption engine may comprise a plurality of encryption pipelines to respectively encrypt a plurality of video sub-streams partitioned from the video stream in parallel in a single pass as the video sub-streams are being generated. The plurality of encryption pipelines may use a corresponding plurality of multi-part encryption counters to encrypt the corresponding video sub-streams as the video sub-streams are being generated. Each of the multi-part encryption counters used by one of the encryption pipelines may comprise a sub-portion that remains constant while encoding the corresponding video sub-stream, but the sub-key is unique for the one encryption pipeline, and differs from corresponding sub-portions of the multi-part encryption counters used by the other encryption pipelines. Other embodiments may be disclosed or claimed.

公开(公告)号：US20180341496A1

公开(公告)日：2018-11-29

申请号：US15605070

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Ned M. Smith ,  Rajesh Poornachandran ,  Simon Hunt ,  Priyadarsini Devanand

IPC: G06F9/44 ,  G06F15/78 ,  G06F9/50

Abstract: A method dynamically reconfigures a system on a chip (SOC) comprising multiple semiconductor intellectual property (IP) blocks. The method comprises, when booting a data processing system (DPS) comprising the SOC, automatically allocating different IP blocks to multiple different microsystems within the DPS, based on a static partitioning policy (SPP). The method also comprises, after booting the DPS, determining that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) a dynamic partitioning policy (DPP). The method also comprises, in response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocating at least one of the IP blocks from one of the microsystems to another of the microsystems without resetting at least one of the microsystems. Other embodiments are described and claimed.

公开(公告)号：US08942376B2

公开(公告)日：2015-01-27

申请号：US13804780

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Priyadarsini Devanand

IPC: H04L29/02 ,  G06F21/60 ,  H04L29/06 ,  H04N21/4363 ,  H04N21/4367 ,  H04L9/32 ,  H04L15/24

CPC classification number: G06F21/60 ,  H04L9/321 ,  H04L63/10 ,  H04L63/20 ,  H04L2463/101 ,  H04N21/43635 ,  H04N21/4367

Abstract: In one embodiment of the invention, a format for renewability content (e.g., a System Renewability Message (SRM)) corresponding to a content protection protocol (e.g., High-Bandwidth Digital Content Protection (HDCP)) may be interoperable with devices that are compliant with different versions of the standard (e.g., HDCP1.x and 2.x devices) and that include different amounts of storage for the renewability content (e.g., first and second generation devices).

Abstract translation: 在本发明的一个实施例中，对应于内容保护协议（例如，高带宽数字内容保护（HDCP））的可再生性内容（例如，系统可再生消息（SRM））的格式可以与符合标准的设备互操作 具有不同版本的标准（例如，HDCP1.x和2.x设备），并且包括可再生能力内容的不同数量的存储（例如，第一和第二代设备）。

公开(公告)号：US20150121074A1

公开(公告)日：2015-04-30

申请号：US14507903

申请日：2014-10-07

Applicant: Intel Corporation

Inventor： Priyadarsini Devanand ,  Gary L. Graunke

IPC: H04L29/06

CPC classification number: H04L63/0428 ,  H04L9/0631 ,  H04L9/08 ,  H04L9/0822 ,  H04L9/0825 ,  H04L9/3236 ,  H04L63/061 ,  H04L2209/12 ,  H04L2209/603

Abstract: An embodiment of the invention includes a processing system to provide protected digital content, the processing system comprising a processor and control logic which, when used by the processor, results in the processing system performing operations comprising determining first and second receivers, which are coupled to the processing system, are within a predetermined acceptable proximity to the processing system. The processing system is upstream to the first receiver and the first receiver is upstream to the second receiver. Other embodiments are provided herein.

Abstract translation: 本发明的实施例包括提供受保护的数字内容的处理系统，所述处理系统包括处理器和控制逻辑，所述处理器和控制逻辑在处理器使用时导致处理系统执行包括确定第一和第二接收器的操作， 处理系统处于预定的可接近的处理系统附近。 处理系统在第一接收器的上游，第一接收器在第二接收器的上游。 本文提供了其他实施例。

公开(公告)号：US10552168B2

公开(公告)日：2020-02-04

申请号：US15605070

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Barry E. Huntley ,  Ned M. Smith ,  Rajesh Poornachandran ,  Simon Hunt ,  Priyadarsini Devanand

IPC: G06F9/44 ,  G06F15/78 ,  G06F21/57 ,  G06F9/4401 ,  G06F9/50

Abstract: A method dynamically reconfigures a system on a chip (SOC) comprising multiple semiconductor intellectual property (IP) blocks. The method comprises, when booting a data processing system (DPS) comprising the SOC, automatically allocating different IP blocks to multiple different microsystems within the DPS, based on a static partitioning policy (SPP). The method also comprises, after booting the DPS, determining that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) a dynamic partitioning policy (DPP). The method also comprises, in response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocating at least one of the IP blocks from one of the microsystems to another of the microsystems without resetting at least one of the microsystems. Other embodiments are described and claimed.

公开(公告)号：US10164947B2

公开(公告)日：2018-12-25

申请号：US14507903

申请日：2014-10-07

Applicant: Intel Corporation

Inventor： Priyadarsini Devanand ,  Gary L. Graunke

IPC: H04L9/32 ,  H04L29/06 ,  H04L9/06 ,  H04L9/08

Abstract: An embodiment of the invention includes a processing system to provide protected digital content, the processing system comprising a processor and control logic which, when used by the processor, results in the processing system performing operations comprising determining first and second receivers, which are coupled to the processing system, are within a predetermined acceptable proximity to the processing system. The processing system is upstream to the first receiver and the first receiver is upstream to the second receiver. Other embodiments are provided herein.