公开(公告)号：US20200005866A1

公开(公告)日：2020-01-02

申请号：US16023728

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Umut Arslan ,  Fatih Hamzaoglu

IPC: G11C13/00 ,  G11C7/06 ,  G11C8/10

Abstract: Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.

公开(公告)号：US09281043B1

公开(公告)日：2016-03-08

申请号：US14582745

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Pulkit Jain ,  Fatih Hamzaoglu ,  Liqiong Wei

IPC: G11C11/00 ,  G11C11/16 ,  G06F12/02 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

Abstract translation: 描述了包括位线的装置。 该装置还包括耦合到位线的第一和第二存储单元。 第一存储单元具有第一存取晶体管。 第一存取晶体管耦合到第一线电阻。 第二存储单元具有第二存取晶体管。 第二存取晶体管耦合到第二线路电阻。 第二线电阻大于第一线电阻。 该装置还包括耦合到位线的第一和第二驱动器。 第二个驱动程序是比第一个驱动程序更强大的驱动程序。 该装置还包括选择第一驱动器以将信息写入第一存储单元并选择第二驱动器以将信息写入第二存储单元的电路。

公开(公告)号：US20220415896A1

公开(公告)日：2022-12-29

申请号：US17358930

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Pulkit Jain ,  James Waldemer ,  Mark Armstrong ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

公开(公告)号：US10573809B2

公开(公告)日：2020-02-25

申请号：US16077571

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC: H01L45/00

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

公开(公告)号：US10515697B1

公开(公告)日：2019-12-24

申请号：US16023728

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Umut Arslan ,  Fatih Hamzaoglu

IPC: G11C13/00 ,  G11C7/06 ,  G11C8/10

Abstract: Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.

公开(公告)号：US20190036020A1

公开(公告)日：2019-01-31

申请号：US16077571

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Uday Shah ,  Elijah V. Karpov ,  Niloy Mukherjee ,  Pulkit Jain ,  Aravind S. Killampalli ,  Jay P. Gupta ,  James S. Clarke

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1641

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

公开(公告)号：US20230397410A1

公开(公告)日：2023-12-07

申请号：US17834679

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Juan Alzate Vinasco ,  Liqiong Wei ,  Ozdemir Akin ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4091

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  G11C11/4085 ,  G11C11/4091

Abstract: Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die. In an embodiment, a differential sense amplifier of the IC die is coupled to a first array and a second array via a first bit line and a second bit line, respectively. The first bit line and the second bit line extend from a first level of BEOL memory arrays, toward a front end of line (FEOL) of the IC die, on opposite respective sides of first array, wherein the differential sense amplifier is in a footprint region for the first memory array. In another embodiment, a word line driver circuit comprises a two stage charger-discharger circuit which mitigates hot carrier injection.

公开(公告)号：US09922691B2

公开(公告)日：2018-03-20

申请号：US15062073

申请日：2016-03-05

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Fatih Hamzaoglu ,  Liqiong Wei

IPC: G11C11/00 ,  G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659

Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

公开(公告)号：US09805790B2

公开(公告)日：2017-10-31

申请号：US15025229

申请日：2013-12-05

Applicant: Intel Corporation

Inventor： Nathaniel J. August ,  Pulkit Jain ,  Stefan Rusu ,  Fatih Hamzaoglu ,  Rangharajan Venkatesan ,  Muhammad Khellah ,  Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz ,  Yih Wang

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.