公开(公告)号：US20240347514A1

公开(公告)日：2024-10-17

申请号：US18757034

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Naveed Zaman ,  Aravind Dasu ,  Sreedhar Ravipalli ,  Rakesh Cheerla ,  Martin Home

IPC: H01L25/065 ,  H04L9/40 ,  H04L47/10 ,  H04L49/90

CPC classification number: H01L25/0657 ,  H04L47/10 ,  H04L49/90 ,  H04L63/1458

Abstract: A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.

公开(公告)号：US20200328192A1

公开(公告)日：2020-10-15

申请号：US16914164

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Naveed Zaman ,  Aravind Dasu ,  Sreedhar Ravipalli ,  Rakesh Cheerla ,  Martin Horne

IPC: H01L25/065

Abstract: A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.

公开(公告)号：US12046578B2

公开(公告)日：2024-07-23

申请号：US16914164

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Naveed Zaman ,  Aravind Dasu ,  Sreedhar Ravipalli ,  Rakesh Cheerla ,  Martin Horne

IPC: H01L25/065 ,  H04L9/40 ,  H04L47/10 ,  H04L49/90

CPC classification number: H01L25/0657 ,  H04L47/10 ,  H04L49/90 ,  H04L63/1458

Abstract: A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.