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    MEMORYLESS WEIGHT STORAGE HARDWARE FOR NEURAL NETWORKS
    3.
    发明申请
    MEMORYLESS WEIGHT STORAGE HARDWARE FOR NEURAL NETWORKS 审中-公开

    公开(公告)号：US20190042913A1

    公开(公告)日：2019-02-07

    申请号：US15884001

    申请日：2018-01-30

    Applicant: Intel Corporation

    Inventor： Phil Knag ,  Gregory Kengho Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Ram Kumar Krishnamurthy

    IPC: G06N3/04

    Abstract: Various systems, devices, and methods for operating on a data sequence. A system includes a set of circuits that form an input layer to receive a data sequence; first hardware computing units to transform the data sequence, the first hardware computing units connected using a set of randomly selected weights, a first hardware computing unit to: receive an input from a second hardware computing unit, determine a weight of a connection between the first and second hardware computing units using an identifier of the second hardware computing unit and a fixed random weight generator, and operate on the input using the weight to determine a state of the first hardware computing unit; and second hardware computing units to operate on states of the first computing units to generate an output based on the data sequence.

    SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT
    4.
    发明公开
    SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT 审中-公开

    公开(公告)号：US20240204782A1

    公开(公告)日：2024-06-20

    申请号：US18081907

    申请日：2022-12-15

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Ram Kumar Krishnamurthy

    IPC: H03K19/094 ,  H03K19/017 ,  H03K19/1776

    CPC classification number: H03K19/09425 ,  H03K19/01728 ,  H03K19/1776

    Abstract: Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

    MEMORY TIMING CHARACTERIZATION CIRCUITRY
    6.
    发明公开
    MEMORY TIMING CHARACTERIZATION CIRCUITRY 审中-公开

    公开(公告)号：US20240319269A1

    公开(公告)日：2024-09-26

    申请号：US18124338

    申请日：2023-03-21

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram Kumar Krishnamurthy

    IPC: G01R31/317 ,  G01R31/3185

    CPC classification number: G01R31/31725 ,  G01R31/31713 ,  G01R31/318536

    Abstract: An apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. The plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. The first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. The second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. The third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. The reference delay generator provides a synchronized clock signal to the flip-flop circuits.

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