公开(公告)号：WO2018063746A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/049994

申请日：2017-09-03

Applicant: INTEL CORPORATION

Inventor： YOON, Jh ,  SHE, Yong ,  GUO, Mao ,  PATTEN, Richard

IPC: H01L23/538 ,  H01L25/065

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate, an electronic component, a mold compound encapsulating the electronic component, and a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer. The redistribution layer and the package substrate can be electrically coupled. In addition, the redistribution layer and the electronic component can be electrically coupled to electrically couple the electronic component and the package substrate. Associated systems and methods are also disclosed.

Abstract translation: 披露了电子器件封装技术。 根据本公开的电子器件封装可以包括封装衬底，电子部件，封装电子部件的模制化合物以及布置为使得模制化合物位于封装衬底和再分布层之间的再分布层。 再分布层和封装衬底可以电耦合。 此外，再分布层和电子组件可以电耦合以电耦合电子组件和封装衬底。 还公开了相关的系统和方法。

公开(公告)号：WO2018112914A1

公开(公告)日：2018-06-28

申请号：PCT/CN2016/111785

申请日：2016-12-23

Applicant: INTEL CORPORATION

Inventor： DING, Zhicheng ,  SHE, Yong ,  LIU, Bin ,  TAN, Aiping ,  DENG, Li

IPC: H01L25/065 ,  H01L23/00

Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

公开(公告)号：WO2018058548A1

公开(公告)日：2018-04-05

申请号：PCT/CN2016/101130

申请日：2016-09-30

Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  TAN, Aiping ,  DENG, Li

IPC: H01L25/00

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract translation: 封装中的系统包括相对于处理器裸片垂直堆叠的阶梯式堆叠式存储器模块。 邻近处理器芯片使用垫片为阶梯堆叠的内存模块创建桥接。 楼梯式堆叠存储器模块中的每个存储器裸片包括从矩阵中露出的用于连接的垂直接合线。 矩阵包围阶梯式堆叠的存储器模块和至少一部分处理器裸片。

公开(公告)号：WO2020168552A1

公开(公告)日：2020-08-27

申请号：PCT/CN2019/075875

申请日：2019-02-22

Applicant: INTEL CORPORATION ,  TANG, Xiaoying ,  DING, Zhicheng ,  BIN, Liu ,  SHE, Yong ,  XU, Zhijun

Inventor： TANG, Xiaoying ,  DING, Zhicheng ,  BIN, Liu ,  SHE, Yong ,  XU, Zhijun

IPC: H01L23/488

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

公开(公告)号：WO2020118558A1

公开(公告)日：2020-06-18

申请号：PCT/CN2018/120572

申请日：2018-12-12

Applicant: INTEL CORPORATION ,  DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  XU, Zhijun

Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  XU, Zhijun

IPC: H01L23/525

Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

公开(公告)号：WO2019066960A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054588

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： GOGINENI, Sireesha ,  KIM, Andrew ,  SHE, Yong ,  BLUE, Karissa J.

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/12 ,  H01L23/00

Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.

公开(公告)号：WO2018063744A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/049991

申请日：2017-09-03

Applicant: INTEL CORPORATION

Inventor： MEYERS, John G. ,  KIM, Hyoung Il ,  SHE, Yong

IPC: H01L23/544 ,  H01L25/065

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a plurality of dies (104) stacked on a substrate (102) and a reference die (106) on the plurality of dies and having a fiducial marker (108) that indicates a spatial position of the plurality of dies for alignment of an electronics assembly tool (110). The fiducial marker can comprise a physical alteration of the reference die, such as indicia that is sawed or laser/plasma/chemical etched. A transparent dielectric layer (120) is disposed on the reference die such that the tool can locate the fiducial marker in three dimensional space through the transparent layer. The dielectric layer is etched corresponding to a photomask after a photoresist is disposed on the dielectric layer. The etched dielectric layer comprises at least one redistribution layer (116) electrically coupled to the vertical wire interconnect structure (112) to provide an ultra-thin package. A method of aligning an electronics assembly tool is disclosed.

Abstract translation: 披露了电子器件封装技术。 在一个示例中，电子设备包括堆叠在多个管芯上的衬底（102）和参考管芯（106）上的多个管芯（104），并且具有指示多个管芯的空间位置的基准标记（108） 用于对准电子组装工具（110）的模具。 基准标记可以包括参考裸片的物理变化，诸如锯切或激光/等离子体/化学蚀刻的标记。 透明介电层（120）设置在参考裸片上，使得工具可以通过透明层将三维空间中的基准标记定位。 在电介质层上设置光刻胶之后，对与光掩模对应的电介质层进行刻蚀。 蚀刻的介电层包括电耦合到垂直导线互连结构（112）的至少一个再分布层（116）以提供超薄封装。 公开了一种对准电子组装工具的方法。

公开(公告)号：WO2018161347A1

公开(公告)日：2018-09-13

申请号：PCT/CN2017/076286

申请日：2017-03-10

Applicant: INTEL CORPORATION

Inventor： SHE, Yong ,  LIU, Bin ,  DING, Zhicheng ,  TAN, Aiping

IPC: H05K7/20

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：WO2018125254A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069644

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： DING, Zhicheng ,  LIU, Bin ,  SHE, Yong ,  KIM, Hyoung Il

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include an electronic component, a redistribution layer, and an interposer electrically coupling the redistribution layer and the electronic component. The interposer can have interconnect interfaces on a top side electrically coupled to the electronic component and interconnect interfaces on a bottom side electrically coupled to the redistribution layer. A density of the interconnect interfaces on the top side can be greater than a density of the interconnect interfaces on the bottom side. Associated systems and methods are also disclosed.

公开(公告)号：WO2018112687A1

公开(公告)日：2018-06-28

申请号：PCT/CN2016/110701

申请日：2016-12-19

Applicant: INTEL CORPORATION ,  LIU, Bin ,  DING, Zhicheng ,  SHE, Yong ,  TAN, Aiping ,  GUO, Mao

Inventor： LIU, Bin ,  DING, Zhicheng ,  SHE, Yong ,  TAN, Aiping ,  GUO, Mao

IPC: H01L25/00

Abstract: Disclosed herein are integrated circuit (IC) die stacks, as well as related apparatuses and methods. For example, in some embodiments, an IC package may include: a package substrate having a substrate conductive contact; a first die coupled to the package substrate, wherein the first die has a first face and an opposing second face, the second face of the first die is between the first face of the first die and the package substrate, and the first die has a first conductive contact at the first face of the first die; a second die coupled to the first die, wherein the second die has a second conductive contact facing the first face of the first die; and a bondwire between the first conductive contact and the substrate conductive contact, wherein the bondwire is also in electrical contact with the second conductive contact.