公开(公告)号：US20230297419A1

公开(公告)日：2023-09-21

申请号：US17699992

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Karthik VAIDYANATHAN ,  Sreedhar CHALASANI ,  Vasanth RANGANATHAN

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC classification number: G06F9/4881 ,  G06F9/505 ,  G06F9/5016 ,  G06F12/0891

Abstract: Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.