公开(公告)号：US20230095191A1

公开(公告)日：2023-03-30

申请号：US17485149

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Koustav Ganguly ,  Ryan Keech ,  Anand Murthy ,  Mohammad Hasan ,  Pratik Patel ,  Tahir Ghani ,  Subrina Rafique

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66

Abstract: Methods, transistors, and systems are discussed related to anisotropically etching back deposited epitaxial source and drain semiconductor materials for reduced lateral source and drain spans in the fabricated transistors. Such lateral width reduction of the source and drain materials enables improved transistor scaling and perturbation reduction in the resultant source and drain semiconductor materials.

公开(公告)号：US20230282718A1

公开(公告)日：2023-09-07

申请号：US17687463

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Mohammad Hasan ,  Tahir Ghani ,  Charles H. Wallace

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

Abstract: Techniques are provided herein to form semiconductor devices having different pitches, yet maintaining a substantially similar depth to the diffusion regions between the semiconductor regions. In an example, a row of semiconductor devices having semiconductor regions extending in a first direction can include some devices having a diffusion region with a first width in the first direction and some devices having a diffusion region with a second width in the first direction, where the second width is different from the first width. The depths of the diffusion regions having both the first and second widths may be substantially similar (e.g., within 2 nm or less of one another). In some examples, the bottom surface of at least one of the wider diffusion regions has a step profile.

公开(公告)号：US20230079586A1

公开(公告)日：2023-03-16

申请号：US17473431

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Mohammad Hasan ,  Tahir Ghani ,  Pratik A. Patel ,  Leonard P. Guler ,  Mohit K. Haran ,  Clifford L. Ong

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.

公开(公告)号：US20250006737A1

公开(公告)日：2025-01-02

申请号：US18216520

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Aryan Navabi-Shirazi ,  Michael Babb ,  Kai Loon Cheong ,  Cheng-Ying Huang ,  Mohammad Hasan ,  Leonard P. Guler ,  Marko Radosavljevic

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A material stack comprising a plurality of bi-layers, each bi-layer comprising two semiconductor material layers, is fabricated into a transistor structure including a first stack of channel materials that is coupled to an n-type source and drain and in a vertical stack with a second stack of channel materials that is coupled to a p-type source drain. Within the first stack of channel material layers a first of two semiconductor material layers may be replaced with a first gate stack while within the second stack of channel materials a second of two semiconductor material layers may be replaced with a second gate stack.

公开(公告)号：US12176408B2

公开(公告)日：2024-12-24

申请号：US17131467

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Willy Rachmady ,  Hsin-Fen Li ,  Christopher Parker ,  Prashant Wadhwa ,  Tahir Ghani ,  Mohammad Hasan ,  Jianqiang Lin

IPC: H01L29/423 ,  B82Y10/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B61/00 ,  H10B63/00

Abstract: A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

公开(公告)号：US20230209798A1

公开(公告)日：2023-06-29

申请号：US17560913

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohammad Hasan ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/1108 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/42392

Abstract: Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

公开(公告)号：US20230197818A1

公开(公告)日：2023-06-22

申请号：US17559342

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  William Hsu ,  Mohammad Hasan ,  Ritesh Das ,  Vivek Thirtha ,  Biswajeet Guha ,  Oleg Golonzka

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

公开(公告)号：US20230084182A1

公开(公告)日：2023-03-16

申请号：US17473427

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Mohammad Hasan ,  Tahir Ghani ,  Pratik A. Patel ,  Mohit K. Haran ,  Leonard P. Guler ,  Clifford L. Ong

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

Abstract: Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device may be a GAA transistor with a first number of semiconductor nanoribbons while the n-channel device may be a GAA transistor with a second number of semiconductor nanoribbons that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

公开(公告)号：US12288808B2

公开(公告)日：2025-04-29

申请号：US18370586

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Anand S. Murthy ,  Nicholas G. Minutillo ,  Suresh Vishwanath ,  Mohammad Hasan ,  Biswajeet Guha ,  Subrina Rafique

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US11990472B2

公开(公告)日：2024-05-21

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Michael K. Harper ,  William Hsu ,  Biswajeet Guha ,  Tahir Ghani ,  Niels Zussblatt ,  Jeffrey Miles Tan ,  Benjamin Kriegel ,  Mohit K. Haran ,  Reken Patel ,  Oleg Golonzka ,  Mohammad Hasan

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.