公开(公告)号：US20190206753A1

公开(公告)日：2019-07-04

申请号：US15859483

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Mohit MAMODIA ,  Paul START ,  Ken HACKENBERG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L23/29 ,  H01L25/07

CPC classification number: H01L23/3114 ,  H01L23/291 ,  H01L23/49506 ,  H01L23/562 ,  H01L25/074

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package including a die on a substrate, where the die has a front side surface electrically coupled to the substrate and a backside surface that is opposite from the front side surface. The semiconductor package also has a bicontinuous ceramic composite (BCC) stiffener on the backside surface of the die. The BCC stiffener may include one or more materials, including porous ceramics, polymeric resins, and metals. The BCC stiffener may be directly coupled to the backside surface of the die without an adhesive layer. The BCC stiffener may be disposed on the die to reduce warpage based on the substrate and die. The semiconductor package may have the BCC stiffener formed with the one or more materials using a polymeric resin in a liquid state process and a resin pre-loaded in a ceramic process.

公开(公告)号：US20180190593A1

公开(公告)日：2018-07-05

申请号：US15396415

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Anna M. PRAKASH ,  Suriyakala RAMALINGAM ,  Boxi LIU ,  Mohit GUPTA ,  Ziv BELMAN ,  Baruch SCHIFFMANN ,  Arnon HIRSHBERG ,  Vladimir MALAMUD ,  Ron WITTENBERG

IPC: H01L23/552 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L23/3142 ,  H01L23/552 ,  H01L24/27 ,  H01L24/32 ,  H01L25/167 ,  H01L25/50 ,  H01L31/107 ,  H01L2224/2731 ,  H01L2224/27318 ,  H01L2224/27418 ,  H01L2224/27505 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83191 ,  H01L2224/8322 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/0133 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1434 ,  H01L2924/3025

Abstract: In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, APDs). In one embodiment, the conductive adhesives can additionally be used for thermal dissipation and for electrical contact in connection with one or more electronic components on a semiconductor package. In one embodiment, various materials including, spray prints, conductive paste, inks (for example, sintering silver-based materials), epoxy material (for example, epoxy materials filled with silver and/or other metal particles) can be used to provide a conductive adhesive layer.

公开(公告)号：US20200005983A1

公开(公告)日：2020-01-02

申请号：US16024718

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Malavarayan SANKARASUBRAMANIAN ,  Yongki MIN ,  Anne AUGUSTINE ,  Kaladhar RADHAKRISHNAN ,  Taylor GAINES ,  Ziyin LIN

IPC: H01F27/02 ,  H01F1/42 ,  H01F41/00 ,  H01F1/01 ,  H01L25/16 ,  H01L21/48 ,  H01F27/29

Abstract: Embodiments herein relate to a magnetic encapsulant composite, comprising a mixture of a first material that is a soft magnetic filler, a second material that is a polymer matrix, and a third material that is a process ingredient. The magnetic encapsulant composite may then encapsulate or partially encapsulate a magnetic inductor coupled to a substrate to increase the inductance of the magnetic inductor and/or to strengthen the substrate to which the magnetic inductor and the composite are coupled.

公开(公告)号：US20190202136A1

公开(公告)日：2019-07-04

申请号：US15859318

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Mark SALTAS ,  Amram EITAN

IPC: B29C65/48 ,  B29C65/02 ,  C09J9/02 ,  C09J163/00 ,  C09J175/04 ,  C09J5/06 ,  H05K1/18 ,  H05K3/32

CPC classification number: B29C65/4805 ,  B29C65/02 ,  B29L2031/3425 ,  C08K3/02 ,  C08K3/04 ,  C08K2003/023 ,  C08K2003/0806 ,  C08K2003/0812 ,  C08K2201/001 ,  C09J5/06 ,  C09J9/02 ,  C09J163/00 ,  C09J175/04 ,  C09J2205/31 ,  C09J2400/10 ,  C09J2400/16 ,  C09J2463/00 ,  C09J2475/00 ,  H05K1/181 ,  H05K3/321 ,  H05K2201/0215 ,  H05K2203/166

Abstract: Apparatuses, systems and methods associated with procedures and adhesive elements for affixing components together are disclosed herein. In embodiments, an assembly may include a first component and a second component coupled to the first component. The assembly may further include a plurality of adhesive elements located between the first component and the second component, wherein the plurality of adhesive elements couple the second component to the first component, and wherein each adhesive element of the plurality of adhesive elements is equidistance from adjacent adhesive elements of the plurality of adhesive elements. Other embodiments may be described and/or claimed.

公开(公告)号：US20180342463A1

公开(公告)日：2018-11-29

申请号：US16035048

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Anna M. PRAKASH ,  Suriyakala RAMALINGAM ,  Boxi LIU ,  Mohit GUPTA ,  Ziv BELMAN ,  Baruch SCHIFFMANN ,  Arnon HIRSHBERG ,  Vladimir MALAMUD ,  Ron WITTENBERG

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L31/107 ,  H01S5/022

Abstract: In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, APDs). In one embodiment, the conductive adhesives can additionally be used for thermal dissipation and for electrical contact in connection with one or more electronic components on a semiconductor package. In one embodiment, various materials including, spray prints, conductive paste, inks (for example, sintering silver-based materials), epoxy material (for example, epoxy materials filled with silver and/or other metal particles) can be used to provide a conductive adhesive layer.

公开(公告)号：US20210066152A1

公开(公告)日：2021-03-04

申请号：US16557891

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Elizabeth NOFEN ,  Vipul MEHTA ,  Taylor GAINES

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/67 ,  H01L23/373 ,  H01L23/367

Abstract: A device is disclosed. The device includes a first die, a plurality of chiplets above the first die, a first underfill material beneath the chiplets, and a gap fill material between the chiplets. The gap fill material is different from the first underfill material. An interface region is formed between the first underfill material and the gap fill material

公开(公告)号：US20200006169A1

公开(公告)日：2020-01-02

申请号：US16022528

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： William WARREN ,  Taylor GAINES ,  Frederick ATADANA ,  Edvin CETEGEN ,  Vipul MEHTA ,  Hsin-Yu LI ,  Yuying WEI ,  Yang GUO ,  Ren ZHANG

IPC: H01L23/16 ,  H01L23/31

Abstract: A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.