公开(公告)号：US20240071831A1

公开(公告)日：2024-02-29

申请号：US17896813

申请日：2022-08-26

Applicant: INTEL CORPORATION

Inventor： Chang Wan Han ,  Biswajeet Guha ,  Vivek Thirtha ,  William Hsu ,  Ian Yang ,  Oleg Golonzka ,  Kevin J. Fischer ,  Suman Dasgupta ,  Sameerah Desnavi ,  Deepak Sridhar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure

公开(公告)号：US11594637B2

公开(公告)日：2023-02-28

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Stephen Snyder ,  Biswajeet Guha ,  William Hsu ,  Urusa Alaan ,  Tahir Ghani ,  Michael K. Harper ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20230197818A1

公开(公告)日：2023-06-22

申请号：US17559342

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  William Hsu ,  Mohammad Hasan ,  Ritesh Das ,  Vivek Thirtha ,  Biswajeet Guha ,  Oleg Golonzka

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

公开(公告)号：US11569370B2

公开(公告)日：2023-01-31

申请号：US16454408

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar ,  Biswajeet Guha ,  William Hsu ,  Dax Crum ,  Oleg Golonzka ,  Tahir Ghani ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/06 ,  H01L21/3105

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.