公开(公告)号：US20250006721A1

公开(公告)日：2025-01-02

申请号：US18215514

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Douglas Stout ,  Tai-Hsuan Wu ,  Xinning Wang ,  Ruth Brain ,  Chin-Hsuan Chen ,  Sivakumar Venkataraman ,  Quan Shi ,  Nikolay Ryzhenko Vladimirovich

IPC: H01L27/02 ,  G06F30/392 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

公开(公告)号：US20240202415A1

公开(公告)日：2024-06-20

申请号：US18068601

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Quan Shi ,  Patrick Morrow ,  Charles Henry Wallace ,  Lars Liebmann ,  Thi Nguyen ,  Sivakumar Venkataraman ,  Nikolay Ryzhenko Vladimirovich ,  Xinning Wang ,  Douglas Stout

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.

公开(公告)号：US20240113104A1

公开(公告)日：2024-04-04

申请号：US17936952

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Tahir Ghani ,  Xinning Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203

Abstract: Techniques are provided to form semiconductor devices that include a gate cut that passes through a plurality of semiconductor bodies (e.g., nanoribbons or nanosheets) such that the gate cut acts as a dielectric spine in a forksheet arrangement with the semiconductor bodies on either side of the gate cut. In an example, two semiconductor devices in a forksheet arrangement include semiconductor bodies directly on either side of a dielectric spine. A gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) that extends around each of the semiconductor bodies of both semiconductor devices. The dielectric spine interrupts the entire height of the gate structure between the two devices and includes dielectric material (e.g., low-k dielectric), and the gate dielectric of the gate structure is not present along sidewalls of the spine between adjacent bodies.

公开(公告)号：US20240429161A1

公开(公告)日：2024-12-26

申请号：US18213963

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Tai-Hsuan Wu ,  Nikolay Ryzhenko Vladimirovich ,  Anand Krishnamoorthy ,  Mikhail Sergeevich Talalay ,  Xinning Wang ,  Quan Shi ,  Ozdemir Akin

IPC: H01L23/528 ,  H01L23/522

Abstract: Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.

公开(公告)号：US12051692B2

公开(公告)日：2024-07-30

申请号：US17176412

申请日：2021-02-16

Applicant: Intel Corporation

Inventor： Quan Shi ,  Sukru Yemenicioglu ,  Marni Nabors ,  Nikolay Ryzhenko ,  Xinning Wang ,  Sivakumar Venkataraman

IPC: H01L27/088 ,  H01L23/50 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L23/50 ,  H01L29/0669 ,  H01L29/785 ,  H01L2029/7858

Abstract: Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.

公开(公告)号：US20240113177A1

公开(公告)日：2024-04-04

申请号：US17957887

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Quan Shi ,  Marni Nabors ,  Charles H. Wallace ,  Xinning Wang ,  Tahir Ghani ,  Andy Chih-Hung Wei ,  Mohit K. Haran ,  Leonard P. Guler ,  Sivakumar Venkataraman ,  Reken Patel ,  Richard Schenker

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: An integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. A conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. A dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. In an example, each of the first and second devices is a gate-all-around (GAA) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finFet structure having a fin-based channel region.

公开(公告)号：US20240113107A1

公开(公告)日：2024-04-04

申请号：US17957821

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Tahir Ghani ,  Marni Nabors ,  Xinning Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696 ,  H01L29/66795 ,  H01L29/7851

Abstract: An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.