公开(公告)号：US20220300795A1

公开(公告)日：2022-09-22

申请号：US17836523

申请日：2022-06-09

Applicant: Intel Corporation

Inventor： Yash Akhauri ,  Nilesh Jain ,  Pasquale Cocchini ,  Eriko Nurvitadhi

IPC: G06N3/063 ,  G06F17/16

Abstract: Systems, apparatuses and methods may provide for technology that includes a performance-enhanced decompression pipeline having first decoder hardware to convert variable length weights to fixed length keys, wherein the variable length weights are non-uniform quantization values, and second decoder hardware to convert the fixed length keys to bit value. In one example, the first length keys are compressed representations of the variable length weights and the bit values are bit accurate representations of the fixed length keys.

公开(公告)号：US20220114495A1

公开(公告)日：2022-04-14

申请号：US17558284

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Rajesh Poornachandran ,  Abhijit Davare ,  Nilesh Jain ,  Chaunte Lacewell ,  Anahita Bhiwandiwalla ,  Juan Pablo Munoz ,  Andrew Boutros ,  Yash Akhauri

IPC: G06N20/00 ,  G06N5/02 ,  G06F17/16 ,  G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for composable machine learning compute nodes. An example apparatus includes interface circuitry to receive a workload, instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to generate a first configuration of one or more machine-learning models based on a workload, generate a second configuration of hardware, determine an evaluation parameter based on an execution of the workload, the execution of the workload based on the first configuration and the second configuration, and, in response to the evaluation parameter satisfying a threshold, execute the one or more machine-learning models in the first configuration on the hardware in the second configuration, the one or more machine-learning models and the hardware to execute the workload.

公开(公告)号：US20220108054A1

公开(公告)日：2022-04-07

申请号：US17552955

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Yash Akhauri ,  Nilesh Jain ,  Juan Pablo Munoz Chiabrando ,  Adithya M. Niranjan

IPC: G06F30/27

Abstract: An architecture search system evaluates a search space of neural network and hardware architectures with a plurality of candidate controllers. Each controller attempts to identify an optimized architecture using a different optimization algorithm. To identify a controller for the search space, the architecture search system samples subspaces of the search space having a portion of the neural network search space and a portion of the hardware search space. For each subspace, candidate controllers are scored with respect to the optimized design determined by the respective candidate controllers. Using the scores for the various candidate controllers across the sampled subspaces, a controller is selected to optimize the overall network architecture search space.