公开(公告)号：US11322431B2

公开(公告)日：2022-05-03

申请号：US16745920

申请日：2020-01-17

Applicant: J-Devices Corporation

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US20170263537A1

公开(公告)日：2017-09-14

申请号：US15446426

申请日：2017-03-01

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US10559523B2

公开(公告)日：2020-02-11

申请号：US16053965

申请日：2018-08-03

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US20180342443A1

公开(公告)日：2018-11-29

申请号：US16053965

申请日：2018-08-03

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

公开(公告)号：US10062638B2

公开(公告)日：2018-08-28

申请号：US15446426

申请日：2017-03-01

Applicant: J-DEVICES CORPORATION

Inventor： Masafumi Suzuhara

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49565 ,  H01L23/49582

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.