公开(公告)号：US10548219B2

公开(公告)日：2020-01-28

申请号：US15768252

申请日：2016-10-14

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Masao Nakajima ,  Ichiro Amimori ,  Osamu Sawanobori ,  Takao Someya

IPC: H05K1/03 ,  H05K1/11 ,  H05K1/14

Abstract: The present invention provides a stress relaxation substrate for relaxing stress generated due to differences in the hardness of a circuit substrate and a cloth body. This stress relaxation substrate is disposed between a cloth body and a circuit board having a wiring, wherein the stress relaxation substrate includes a stress relaxation layer harder than the cloth body, and softer than the circuit board, an adhesive layer provided on one surface of the stress relaxation layer, and a conductive portion provided on the stress relaxation layer to be formed between a first surface and a second surface.

公开(公告)号：US10966316B2

公开(公告)日：2021-03-30

申请号：US15767227

申请日：2016-10-14

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Masao Nakajima ,  Ichiro Amimori ,  Osamu Sawanobori ,  Takao Someya

IPC: H05K1/03 ,  H05K1/02 ,  H01L23/12 ,  H01L23/14 ,  A61B5/00 ,  A61B5/0205 ,  H01L23/13 ,  A41D1/00

Abstract: A wiring film is provided between a cloth and an electronic component, wherein the wiring film has a wiring layer including an extensible film and wirings provided along the extensible film inside or on an outer surface of the extensible film and at least a part of the wirings is exposed from a first surface of the wiring layer that faces the electronic component.

公开(公告)号：US20190075652A1

公开(公告)日：2019-03-07

申请号：US15767227

申请日：2016-10-14

Applicant: Japan Science and Technology Agency

Inventor： Masao Nakajima ,  Ichiro Amimori ,  Osamu Sawanobori ,  Takao Someya

IPC: H05K1/03 ,  H01L23/13 ,  H01L23/14

Abstract: A wiring film is provided between a cloth and an electronic component, wherein the wiring film has a wiring layer including an extensible film and wirings provided along the extensible film inside or on an outer surface of the extensible film and at least a part of the wirings is exposed from a first surface of the wiring layer that faces the electronic component.

公开(公告)号：US10398377B2

公开(公告)日：2019-09-03

申请号：US15756410

申请日：2016-08-31

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Ichiro Amimori ,  Masao Nakajima ,  Takao Someya

IPC: A61B5/06 ,  A61B5/00 ,  H05K1/18 ,  A61B5/11 ,  H05K1/03 ,  H05K1/11 ,  H04Q9/00 ,  A41D1/00

Abstract: A connector substrate includes a base material, n first input terminals of m groups (m and n are an integer equal to or greater than 2) which are provided on the base material, n first output terminals which are provided on the base material, first wiring patterns which are disposed on or inside the base material and connect the first input terminals and the first output terminals, m second input terminals which are provided on the base material, m second output terminals which are provided on the base material, and second wiring patterns which are disposed on or inside the base material and connect the second input terminals and the second output terminals, in which a first end of each connector wiring constituting the first wiring pattern is connected to one of the n first input terminals constituting each group, and a second end is connected to one of the first output terminals.