公开(公告)号：US10263634B2

公开(公告)日：2019-04-16

申请号：US15753855

申请日：2016-08-03

Applicant: KAGOSHIMA UNIVERSITY

Inventor： Kenichi Ohhata

IPC: H03M1/56 ,  H03M1/36 ,  G04F10/00 ,  H03M1/14 ,  H03M1/12 ,  H03M1/10 ,  H03M1/00

Abstract: AD conversion is performed by using a combination of a parallel AD converter that includes a plurality of comparators to compare an input potential of an analog input signal sampled by a track and hold circuit and reference potentials different from one another and determines a value of a predetermined number of bits on the higher-order side of a digital signal and a single-slope AD converter that reduces the input potential of the analog input signal sampled by the track and hold circuit at a constant speed, converts a time taken until the reduced input potential becomes equal to a reference potential corresponding to the value determined by the parallel AD converter to a digital value, and determines a remaining value on the lower-order side of the digital signal, and thereby the number of bits of the single-slope AD converter can be reduced and high-speed AD conversion is enabled with a small area and low power consumption.

公开(公告)号：US20150180494A1

公开(公告)日：2015-06-25

申请号：US14405760

申请日：2013-06-05

Applicant: KAGOSHIMA UNIVERSITY

Inventor： Kenichi Ohhata

IPC: H03M1/00 ,  H03M1/08 ,  H03M1/36

CPC classification number: H03M1/002 ,  G02F7/00 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/0612 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/145 ,  H03M1/361 ,  H03M1/365 ,  H03M7/165

Abstract: A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

Abstract translation: 并行型AD转换器包括：多个比较器，其接收彼此不同的比较参考电位，并比较比较参考电位和接收的模拟输入信号; 编码器，其对所述多个比较器的输出进行编码以输出数字信号; 以及电阻分压基准电压以产生比较参考电位的电阻梯形电路，并且通过每个位于电阻器之间的输出节点将比较参考电位提供给比较器，并且被设计为提供对应于噪声电流的校正电流，比较器 生成电阻梯形电路中比较参考电位的输出节点，从而比较器产生的噪声电流被校正电流偏移，电阻梯形电路中的偏置电流可能会降低，AD转换精度下降 可以抑制。

公开(公告)号：US09118337B2

公开(公告)日：2015-08-25

申请号：US14405760

申请日：2013-06-05

Applicant: KAGOSHIMA UNIVERSITY

Inventor： Kenichi Ohhata

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/36 ,  H03M1/08 ,  G02F7/00 ,  H03M7/16

CPC classification number: H03M1/002 ,  G02F7/00 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/0612 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/145 ,  H03M1/361 ,  H03M1/365 ,  H03M7/165

Abstract: A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

Abstract translation: 并行型AD转换器包括：多个比较器，其接收彼此不同的比较参考电位，并比较比较参考电位和接收的模拟输入信号; 编码器，其对所述多个比较器的输出进行编码以输出数字信号; 以及电阻分压基准电压以产生比较参考电位的电阻梯形电路，并且通过每个位于电阻器之间的输出节点将比较参考电位提供给比较器，并且被设计为提供对应于噪声电流的校正电流，比较器 生成电阻梯形电路中比较参考电位的输出节点，从而比较器产生的噪声电流被校正电流偏移，电阻梯形电路中的偏置电流可能会降低，AD转换精度下降 可以抑制。