公开(公告)号：AU2010293308A1

公开(公告)日：2012-03-29

申请号：AU2010293308

申请日：2010-04-26

Applicant: KIM JONGHAE ,  KIM MICHAEL J

Inventor： KIM JONGHAE ,  KIM TOMMYY

IPC: A23C11/10 ,  A23L5/40 ,  A23L11/00

Abstract: The present invention relates to a method for manufacturing whole soy milk by sterilizing raw beans with the bean skins by heating in a heating chamber, transforming the starch of the beans into soluble dextrin, and then grinding the beans into an ultra-fine powder to be manufactured into whole soy milk. When the starch of the beans is transformed into dextrin by means of the above-described method, whole soy milk which is as smooth as bovine milk can be manufactured, said whole soy milk being easier to digest and having an excellent taste and flavor due to the removal of the inherent fishy taste and grassy flavor or stink of the bean. Also, by using the entire bean including the skin, the problem of waste (i.e. the skin and dregs) generated in traditional soy milk manufacturing processes is resolved, and soy milk yield is greatly improved. Further, a method is provided for manufacturing whole black soybean milk utilizing the quality anticancer ingredients found in black bean skins.

公开(公告)号：CA2774017A1

公开(公告)日：2011-03-17

申请号：CA2774017

申请日：2010-04-26

Applicant: KIM JONGHAE ,  KIM MICHAEL J

Inventor： KIM JONGHAE ,  KIM MICHAEL J

IPC: A23C11/10 ,  A23L5/40 ,  A23L11/00

Abstract: The present invention relates to a method for manufacturing whole soy milk by sterilizing raw beans with the bean skins by heating in a heating chamber, transforming the starch of the beans into soluble dextrin, and then grinding the beans into an ultra-fine powder to be manufactured into whole soy milk. When the starch of the beans is transformed into dextrin by means of the above-described method, whole soy milk which is as smooth as bovine milk can be manufactured, said whole soy milk being easier to digest and having an excellent taste and flavor due to the removal of the inherent fishy taste and grassy flavor or ?stink? of the bean. Also, by using the entire bean including the skin, the problem of waste (i.e. the skin and dregs) generated in traditional soy milk manufacturing processes is resolved, and soy milk yield is greatly improved. Further, a method is provided for manufacturing whole black soybean milk utilizing the quality anticancer ingredients found in black bean skins.

公开(公告)号：MX2012002837A

公开(公告)日：2012-06-28

申请号：MX2012002837

申请日：2010-04-26

Applicant: KIM JONGHAE

Inventor： KIM JONGHAE ,  KIM MICHAEL J

IPC: A23C11/10 ,  A23L5/40 ,  A23L11/00

Abstract: La presente invención se refiere a un método para producir leche de soya entera al esterilizar las semillas naturales con las cascarillas de las semillas mediante calentamiento en una cámara térmica, transformando el almidón de las semillas en dextrina soluble y después triturando las semillas en partículas ultra-finas para producirse como una leche de soya entera. Cuando el almidón de las semillas se transforma en dextrina por medio del método antes descrito, puede producirse la leche de soya entera que es tan suave como la leche bovina, siendo dicha leche de soya entera más fácil de digerir y teniendo un excelente gusto y sabor debido al retiro del inherente sabor a pescado y sabor grasoso o "maloliente" de las semillas. También al utilizar la semilla entera incluyendo la cascarilla, se resuelve el problema de desecho, (es decir la cascarilla y los sedimentos) generado en los procesos tradicionales de producción de leche de soya, y la leche de soya producida se mejora grandemente. Además se proporciona un método para producir leche de semilla de soya negra entera utilizando los ingredientes anti-cáncer de calidad, encontrados en las cascarillas de la semilla negra.

公开(公告)号：EP2471374A4

公开(公告)日：2015-04-01

申请号：EP10815533

申请日：2010-04-26

Applicant: KIM JONGHAE ,  KIM MICHAEL J

Inventor： KIM JONGHAE ,  KIM MICHAEL J

IPC: A23C11/10 ,  A23L5/40 ,  A23L11/00

CPC classification number: A23C11/103

Abstract: The present invention relates to a method for manufacturing whole soy milk by sterilizing raw beans with the bean skins by heating in a heating chamber, transforming the starch of the beans into soluble dextrin, and then grinding the beans into an ultra-fine particle to be manufactured into whole soy milk. When the starch of the beans is transformed into dextrin by means of the above-described method, whole soy milk which is as smooth as bovine milk can be manufactured, said whole soy milk being easier to digest and having an excellent taste and flavor due to the removal of the inherent fishy taste and grassy flavor or "stink' of the beans. Also, by using the entire bean including the skin, the problem of waste (i.e. the skin and dregs) generated in traditional soy milk manufacturing processes is resolved, and soy milk yield is greatly improved. Further, a method is provided for manufacturing whole black soybean milk utilizing the quality anticancer ingredients found in the black bean skins.

公开(公告)号：WO2010135572A2

公开(公告)日：2010-11-25

申请号：PCT/US2010035646

申请日：2010-05-20

Applicant: QUALCOMM INC ,  KIM JONGHAE ,  WANG FENG ,  NOWAK MATTHEW

Inventor： KIM JONGHAE ,  WANG FENG ,  NOWAK MATTHEW

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H03K19/00392 ,  G01R31/318513 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to indentified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias.

Abstract translation: 一种装置包括具有第一总线的第一管芯，具有堆叠在第一管芯上的第二总线的第二管芯，将第一总线连接到第二总线的多个通孔硅通孔以及用于向第二总线发送数据的第一控制逻辑 多个通孔硅通孔。 另外，可选地，第二控制逻辑用于确定非功能性的多个通孔硅通孔的第一组，其中第二控制逻辑被配置为向第一控制逻辑发送信息，该第一控制逻辑识别多个通孔通孔中的第一组， 识别功能性的第二组通孔硅通孔。 也是通过多个通过硅通孔发送信号的方法。

公开(公告)号：WO2010107772A3

公开(公告)日：2011-01-13

申请号：PCT/US2010027450

申请日：2010-03-16

Applicant: QUALCOMM INC ,  KANG WOO TAG ,  KIM JONGHAE ,  SUH JUNGWON

Inventor： KANG WOO TAG ,  KIM JONGHAE ,  SUH JUNGWON

IPC: H01L27/108 ,  H01L27/04

CPC classification number: H01L27/0805 ,  G06F17/5068 ,  H01L28/40 ,  Y10T29/49117

Abstract: Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.

Abstract translation: 公开了具有增加的电容的半导体器件中的电容器的方法和装置。 在特定实施例中，公开了形成电容器的方法。 在第一金属接触元件和第二金属接触元件之间的第一绝缘材料的一部分被去除以形成通道。 在第一金属接触元件和第二金属接触元件之间的通道中沉积第二绝缘材料。

公开(公告)号：WO2013028638A2

公开(公告)日：2013-02-28

申请号：PCT/US2012051626

申请日：2012-08-20

Applicant: QUALCOMM INC ,  ZUO CHENGJIE ,  YUN CHANGHAN ,  KIM JONGHAE

Inventor： ZUO CHENGJIE ,  YUN CHANGHAN ,  KIM JONGHAE

IPC: H03H9/02

CPC classification number: H01L41/183 ,  H01L41/277 ,  H03H9/02015 ,  H03H9/02228 ,  Y10T29/42

Abstract: A resonator is described. The resonator includes multiple electrodes. The resonator also includes a composite piezoelectric material. The composite piezoelectric material includes at least one layer of a first piezoelectric material and at least one layer of a second piezoelectric material. At least one electrode is coupled to a bottom of the composite piezoelectric material. At least one electrode is coupled to a top of the composite piezoelectric material.

Abstract translation: 描述谐振器。 谐振器包括多个电极。 谐振器还包括复合压电材料。 复合压电材料包括至少一层第一压电材料和至少一层第二压电材料。 至少一个电极耦合到复合压电材料的底部。 至少一个电极耦合到复合压电材料的顶部。

公开(公告)号：WO2012009588A3

公开(公告)日：2012-04-26

申请号：PCT/US2011044093

申请日：2011-07-15

Applicant: QUALCOMM INC ,  CHANDRASEKARAN ARVIND ,  KIM JONGHAE

Inventor： CHANDRASEKARAN ARVIND ,  KIM JONGHAE

IPC: H01L23/552 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L23/3121 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An electronic package-on-package system with integrated shielding. The package-on-package system includes a first package having a first die and a second package having a second die and a substrate. The system also includes a conductive shield having a first portion and a second portion. The first portion is disposed between the first die and the second die and the second portion is disposed between the substrate and the first portion. The first portion is coupled to the second portion for shielding the first die from the second die.

Abstract translation: 具有集成屏蔽功能的电子封装封装系统。 包装封装系统包括具有第一管芯的第一封装和具有第二管芯和衬底的第二封装。 该系统还包括具有第一部分和第二部分的导电屏蔽。 第一部分设置在第一管芯和第二管芯之间，第二部分设置在基板与第一部分之间。 第一部分耦合到第二部分，用于屏蔽第一模具与第二模具。

公开(公告)号：WO2008122459A3

公开(公告)日：2008-11-27

申请号：PCT/EP2008052021

申请日：2008-02-19

Applicant: IBM ,  IBM UK ,  KIM DAE IK ,  KIM JONGHAE ,  KIM MOON JU ,  MOULIC JAMES RANDAL ,  SONG HONG HUA

Inventor： KIM DAE IK ,  KIM JONGHAE ,  KIM MOON JU ,  MOULIC JAMES RANDAL ,  SONG HONG HUA

IPC: G06F11/00

CPC classification number: G06F11/008

Abstract: Method, system and computer program are provided for continually monitoring reliability of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.

Abstract translation: 提供了方法，系统和计算机程序，用于连续监视数字系统的可靠性，并且如果数字系统操作降级到或超过指定阈值，则发出警告信号。 该技术包括周期性地确定数字系统的最大操作频率，以及产生指示数字系统的可靠性劣化的警告信号，如果以下至少一个：（i）数字系统的测量或估计的最大操作频率 低于数字系统的警告阈值操作频率，其中警告阈值频率大于或等于制造商规定的数字系统的最小操作频率; 或者（ii）数字系统的测量的最大操作频率之间的差异的变化率超过数字系统的可接受的变化率阈值。

公开(公告)号：WO2008037634B1

公开(公告)日：2008-05-15

申请号：PCT/EP2007059858

申请日：2007-09-18

Applicant: IBM ,  IBM UK ,  CHO CHOONGYEUN ,  KIM DAEIK ,  KIM JONGHAE ,  KIM MOON JU ,  PLOUCHART JEAN-OLIVIER ,  TRZCINSKI ROBERT

Inventor： CHO CHOONGYEUN ,  KIM DAEIK ,  KIM JONGHAE ,  KIM MOON JU ,  PLOUCHART JEAN-OLIVIER ,  TRZCINSKI ROBERT

IPC: H01L21/02 ,  G06F17/50 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/64 ,  H01L27/02

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F2017/0073 ,  H01L23/5227 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more of chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract translation: 提供用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积 的设计规则检查规则。 对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。 在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。 在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化芯片产量，芯片性能，芯片制造性和电感器Q因子参数中的一个或多个。