公开(公告)号：US09744624B2

公开(公告)日：2017-08-29

申请号：US14742070

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  Pin-Chung Lin ,  Chen-Rui Tseng ,  Cheng-En Ho ,  Yu-An Chen

IPC: H05K3/46 ,  B23K26/402 ,  H05K3/42 ,  B23K26/382 ,  B23K103/00

CPC classification number: B23K26/402 ,  B23K26/382 ,  B23K26/389 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/30 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0341

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.