-
公开(公告)号：US10548214B2
公开(公告)日：2020-01-28
申请号：US15826694
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer.
-
公开(公告)号：US10455694B2
公开(公告)日：2019-10-22
申请号：US16408431
申请日：2019-05-09
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.
-
3.发明申请公开(公告)号：US20190269008A1
公开(公告)日：2019-08-29
申请号：US16408431
申请日：2019-05-09
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A manufacturing method for a multi-layer circuit board is provided. According to the multi-layer circuit board manufactured by the manufacturing method, the multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.
-
4.发明申请公开(公告)号：US20190059153A1
公开(公告)日：2019-02-21
申请号：US15826692
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
CPC classification number: H05K1/0268 , H05K1/09 , H05K3/064 , H05K3/4644 , H05K3/4661 , H05K3/467 , H05K2201/0302 , H05K2203/072 , H05K2203/0723
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.
-
5.发明授权公开(公告)号：US09831167B1
公开(公告)日：2017-11-28
申请号：US15678130
申请日：2017-08-16
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Shuo-Hsun Chang , Yu-Te Lu , Kuo-Chun Huang
IPC: H01L23/498 , H01L23/31 , H01L23/13 , H01L23/00 , H01L21/56 , H01L23/538 , H01L21/48 , H01L23/367
CPC classification number: H01L23/49833 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/3142 , H01L23/367 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2225/1023 , H01L2225/107 , H01L2924/12042 , H01L2924/15311 , H01L2924/1533 , H01L2924/15787 , H01L2924/18161 , H01L2924/3511 , H05K1/0206 , H05K1/0271 , H05K1/183 , H05K3/4697 , H05K2201/10378 , H05K2201/10734 , H05K2203/061 , H01L2924/00
Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier board in order to form a compound carrier board structure. A die is placed in the opening and bonded to the carrier board. A sealant is filled in a gap between surrounding walls of the opening and the die at a height lower than the die to fixedly place the die within the opening and to leave a non-active surface of the die exposed.
-
Patent Agency Ranking
6.发明授权公开(公告)号：US09754870B2
公开(公告)日：2017-09-05
申请号：US15071368
申请日：2016-03-16
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Shuo-Hsun Chang , Yu-Te Lu , Kuo-Chun Huang
CPC classification number: H01L23/49833 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/13 , H01L23/3114 , H01L23/3128 , H01L23/3142 , H01L23/367 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L24/81 , H01L25/105 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2225/1023 , H01L2225/107 , H01L2924/12042 , H01L2924/15311 , H01L2924/1533 , H01L2924/15787 , H01L2924/18161 , H01L2924/3511 , H05K1/0206 , H05K1/0271 , H05K1/183 , H05K3/4697 , H05K2201/10378 , H05K2201/10734 , H05K2203/061 , H01L2924/00
Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening bonded to a non-conductive film then a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.
-
7.发明授权公开(公告)号：US11044806B2
公开(公告)日：2021-06-22
申请号：US16718100
申请日：2019-12-17
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit structure is disposed on the delivery loading plate through the bottom-layer circuit structure, the delivery loading plate exposes the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board.
-
公开(公告)号：US10334719B2
公开(公告)日：2019-06-25
申请号：US15826692
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a patterned metal-interface layer, a metallic delivery loading plate, an electrical connection layer, a conductive corrosion-barrier layer, a bottom dielectric layer, and a multi-layer circuit structure. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. The delivery loading plate and the patterned metal-interface layer expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally. Hence, costs for figuring out reasons of the unqualified electronic component can be reduced, and responsibilities for the unqualified electrical testing result of the electronic component can be clarified.
-
9.发明申请公开(公告)号：US20190059154A1
公开(公告)日：2019-02-21
申请号：US15826694
申请日：2017-11-30
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Chin-Kuan Liu , Chao-Lung Wang , Shuo-Hsun Chang , Yu-Te Lu , Chin-Hsi Chang
Abstract: A multi-layer circuit board capable of being applied with electrical testing includes a metallic delivery loading plate, a bottom-layer circuit structure, a conductive corrosion-barrier layer, and a multi-layer circuit structure. The bottom-layer circuit structure is overlapping on the delivery loading plate. The conductive corrosion-barrier layer is disposed on the bottom dielectric layer. The multi-layer circuit structure is overlapping on the bottom-layer circuit structure. The top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the inner-layer circuit of the multi-layer circuit structure and the bottom-layer circuit of the bottom-layer circuit structure. The delivery loading plate and the bottom dielectric layer of the bottom-layer circuit structure expose the conductive corrosion-barrier layer. Therefore, before the multi-layer circuit board is packaged, an electrical testing can be applied to the multi-layer circuit board to check if it can be operated normally.
-
10.发明授权公开(公告)号：US09406641B2
公开(公告)日：2016-08-02
申请号：US13938335
申请日：2013-07-10
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yi-Fan Kao , Shuo-Hsun Chang , Yu-Te Lu , Kuo-Chun Huang
CPC classification number: H01L24/81 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/562 , H01L24/16 , H01L25/105 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H01L2924/18161 , H01L2924/3511 , H05K1/0206 , H05K1/0271 , H05K1/183 , H05K3/4697 , H05K2201/10378 , H05K2201/10734 , H05K2203/061 , H01L2924/00 , H01L2224/05599
Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.
Abstract translation: Flip-Chip Chip-Scale封装的复合载体板结构及其制造方法提供了一种具有通孔的翻转区和与非导电膜结合以结合到载体板以形成化合物载体的底板 板结构。 底板由低热膨胀系数材料构成。
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.04 seconds)
