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    Semiconductor device including a plug connected to a bit line and containing tungsten
    1.
    发明授权
    Semiconductor device including a plug connected to a bit line and containing tungsten 有权

    公开(公告)号：US11355512B2

    公开(公告)日：2022-06-07

    申请号：US16800163

    申请日：2020-02-25

    Applicant: Kioxia Corporation

    Inventor： Jun Iijima ,  Masayoshi Tagami ,  Masayuki Kitamura ,  Satoshi Wakatsuki

    IPC: H01L23/532 ,  H01L21/768 ,  H01L27/11575

    Abstract: A semiconductor device includes a substrate, a logic circuit provided on the substrate, a wiring layer including a plurality of wirings that are provided above the logic circuit, a first insulating film below the wiring layer, a plug, and a second insulating film. Each of the wirings contains copper and extends along a surface plane of the substrate in a first direction. The wirings are arranged along the surface plane of the substrate in a second direction different from the first direction. The plug extends through the first insulating film in a third direction crossing the first and second directions and is electrically connected to one of the wirings. The plug contains tungsten. The second insulating film is provided between the first insulating film and the plug.

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12218088B2

    公开(公告)日：2025-02-04

    申请号：US17894219

    申请日：2022-08-24

    Applicant: Kioxia Corporation

    Inventor： Masayoshi Tagami

    IPC: H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H10B43/27

    Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11462496B2

    公开(公告)日：2022-10-04

    申请号：US16952205

    申请日：2020-11-19

    Applicant: Kioxia Corporation

    Inventor： Masayoshi Tagami

    IPC: H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H01L27/11582

    Abstract: In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

    Memory device
    5.
    发明授权
    Memory device 有权

    公开(公告)号：US11270980B2

    公开(公告)日：2022-03-08

    申请号：US16916979

    申请日：2020-06-30

    Applicant: KIOXIA CORPORATION

    Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

    IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

    Semiconductor device and method of manufacturing the same
    6.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US11227857B2

    公开(公告)日：2022-01-18

    申请号：US16809739

    申请日：2020-03-05

    Applicant: Kioxia Corporation

    Inventor： Tomoya Sanuki ,  Masayoshi Tagami

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210082880A1

    公开(公告)日：2021-03-18

    申请号：US16809739

    申请日：2020-03-05

    Applicant: Kioxia Corporation

    Inventor： Tomoya Sanuki ,  Masayoshi Tagami

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

    Memory device
    8.
    发明授权
    Memory device 有权

    公开(公告)号：US12272676B2

    公开(公告)日：2025-04-08

    申请号：US18486194

    申请日：2023-10-13

    Applicant: KIOXIA CORPORATION

    Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

    IPC: H01L29/788 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

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